Design of integrated 16 GHz 2 W tuned RF power amplifier
Abstract： This paper describes the design of an integrated tuned power amplifier specified to operate at Inmarsat satellite uplink frequencies from 16265 to 16605 MHzThe basic topology of the amplifier lies on the parallel tuned inverse class E amplifier that is modified by placing the DCblocking capacitor into a new position and by adjusting the size of the capacitor to improve stability below the desired band Further the new positioning reduces losses between drain and load The high currents flowing in the circuit made it necessary to use wide inductor width and highQ finger capacitors in the onchip resonator The amplifier was implemented as a Gallium Arsenide (GaAs) integrated circuit (IC) that delivered 2 W of output power while the drain efficiency was ca 56Measurements included source and load pulls to further improve the performance of the amplifier and to investigate the stability at small input drive levels
Keywords Inverse class E•Power amplifierSelfoscillation• Bias network
1 Introduction
The usability of traditional linear amplifiers in today’s high power communications systems is limited due to their low efficiency This fact has driven the interest of research towards more efficient amplifiers such as class E [1–3] and inverse class E [4] Also the demand of higher output power means higher peak currents and voltages in the drain or collector circuits This creates high requirements for both maximum breakdown values of the transistor and to the passive circuitry of the monolithic microwave integrated circuit (MMIC) The effect of limited conductivity and limited capability to cope with heat can be minimized through careful design of MMIC Further emerging transistor technologies seem to withstand larger current densities and peak voltages [5] and therefore the choice of technology is increasingly important when designing high power devices
The aim of this paper is to show experiences related to the design of switching high power radio frequency(RF) amplifiers (PA) with integrated output pulse shaping In the second chapter the introduction to class E and inverse class E operation is revisited and the differences between the two topologies are reviewedThe third chapter describes the design of the input and output circuitry stabilizing circuits and provides some tips to minimize timing differences at the input of a multifinger transistor The fourth chapter shows the final schematic and a photo of the implemented chip The measured performance is reported in chapter five by using both basic single tone measurement equipment and a modern load pull system using multipurpose tuners(MPT) The last section provides a summary of the article and discussion of the issues related to stabilizing circuits
2 Class E and inverse class E amplifiers
Class E and inverse class E are regarded as switching amplifiers Ideally in both of them the transistor is driven either on or off and this switching operation
produces a series of voltage and current pulses to the output These pulses are phase shifted and therefore do not overlap with each other Ideal nonoverlap causes the transistor to operate with drain efficiency of 100
Classical class E drain waveforms normalized to DC values of supply current and voltage are shown in Fig1The solid line is normalized drain current waveform and the dashed line is normalized drain voltage The requirement for optimal operation in class E is zero voltage switching (ZVS) where the drain voltage and its derivative goes to zero just before the transistor starts to conduct In inverse class E the waveforms have swapped places so that the solid line waveform in Fig1 is the drain voltage and the dashed line is the drain current The optimal operation is also changed to zerocurrent switching (ZCS) where the current and its derivative goes smoothly to zero before the transistor enters nonconducting phase Advantages of inverse class E over classical realization are that the drain peak voltages are lower than in classical class E and the inductance values in the output circuitry are smaller which can save area in a MMIC chip implementation and can usually give smaller electrical series resistance (ESR) [4] Also the possibility to accommondate series inductance as a part of resonating circuitry is useful since the parasitic reactances can cause undamped resonances to drain waveforms [6 7] These advantages were the reasons for choosing inverse class E topology as a starting point for our investigation However the tuned implementation is not traditional inverse class E although it has similar pulsed operation
3 Design of tuned power amplifier
31 GaAs IC process
The IC process used is a Triquint Semiconductor’s pseudomorphic high electron mobility transistor (pHEMT) process named TQPED The process utilizes both enhancement and depletion mode field effect transistors (FETs) with 05lm length optical lithography gates but in our case we used only depletion mode transistors The available depletion mode transistors have a transition frequency (Ft) of 27 GHz draingate breakdown voltage of15 V and nominal pinchoff point of08 V Transistors models used are TOM3 FET models There are several other features in the process nichrome (NiCr) resistors for precision and bulk for high value resistors high value Metal–Insulator–Metal (MIM) capacitors 1 local and 2thick global metal
layers [8]
32 Design of the resonator
The difference between the original inverse class E in Fig2and the final tuned topology used in our designshown in Fig3 is the location of blocking capacitor Cs
The original placing in Fig2provides the DCblocking to two directions to the output (load) and more important it blocks the direct DCcurrent path through Lp to groundIn our case the blocking capacitor is underneath the resonating circuit as shown in Fig3 where the Cs obstructs the flow of DCcurrent through Lp to ground but not to the output (load) There is a direct way for fundamental current to flow to the output without passing any blocking capacitor The DC blocking capacitor can now be made significantly smaller In our case the reduction was from100 pF to less than 50 pF which means savings in chip area and as a secondary effect the ability to tune a stabilizing trap to wanted frequency (more in chapter 32) while maintaining good amplifier performance The design of the DCblock is now also slightly easier since peak current flowing into the blocking branch is smaller Furthermorethe ESR between drain and load is smaller The fundamental current amplitudes in components Cs andLwere12 and 2 A respectively The total peak currents in the parallel resonator structure can be seen in Fig3
The traditional inverse class E dimensioning [4] for16 GHz and Pout3 W results in large chip area as due to high Q 10 the capacitor Ctot is large (635 pF) and—due to high peak currents (ca 6 A)—the inductor gets physically huge To get reasonable onchip component values the design was gradually deviated from the design procedure in [4] by shifting it towards lower load resistance and Q value and increasing the resonance frequency This ended up in a dimensioning that provides clean nonoverlapping current and voltage pulses reasonable size passives but which is eventually closer to class C–E fundamental load [9] than to original inverse class E The final component values of the simulation with discrete component models and an offchip lowpass impedance matching network to 50Ω resulted in the following dimensioningresistive load 4ΩCtot 30 pFLp022 nHand L so small it could be omitted from the final designCs could be reduced down to 50 pF without affecting the overall performance and it can be used to tune a stabilizing below thecarrier notch as shown later in Fig 8 The overall simulation results with a large switching
transistor (12parallel transistors with 18×50µm05µm fingers) estimated 56 W output power with 72 drain efficiency The challenge was now to maintain as good output power and efficiency while replacing the ideal circuit components with process design kit (PDK) components and while adding some stabilizing circuits to the topologyNext design problem came with the physical design of the inductor Despite the lowered Q value the current amplitude was still so high (42 A peak) that ca 200lmwide metal line was needed for the inductor and to keep the center of the 34turn inductor open it could not be made physically smaller than 04 nH Hence the capacitance Ctot and Q value were further reduced a bit and to reduce resistive losses the capacitance Ctot was split into 12parallel highQ capacitors The drawn layout of the resonator structure was imported into 25D field simulator and Sparameters were simulated and compared with those of the discrete simulation prototype The unloaded phase and magnitude of the impedance data for comparisons from Sparameter simulations are shown in Figs4and5 The phase and magnitude data of a distributed resonator is marked with a dashed line in both figures The phases and magnitudes of the resonators follow almost the same lineWhen the complete amplifier was simulated the drain efficiency was about 70 and output power was about34 W The reduction in output power may be explained by parasitic resistances and by the addition of stabilizing circuits The drain efficiency is surprisingly good despite the somewhat lowered Q and empirical output circuit designThe simulated and implemented distributed resonator is shown in Fig6
33 Stabilizing the amplifier
The amplifier showed a tendency of instability during largesignal Sparameter (LSSP) simulations In the endstability had to be evaluated through LSSPbased stability circles since unconditional stability (K>1) could not be achieved without heavy losses Stability circles were drawn throughout a frequency range of 05–5 GHz After several simulations a variety of stabilizing circuits had to be used to compensate ringing behaviourFirst the discrete capacitor Cs was tuned to 50 pF to generate a trap in the output resonator at about 12 GHz frequency This helped in achieving stability at frequencies below the frequency bandas shown by Rollett’s Kfactor in Fig7 The 50 pF value was chosen for both small degradation in output power and for good stability performance The effect of tuning of the capacitor Cs is shown in Fig 8 where the capacitor is tuned from 30 to 70 pF
Further 5Ωof series resistance was added to three gate lines as shown in Fig 9(b) to keep the amplifier stable with output standing wave ratio (SWR) range of 461 Also a wideband RCsink circuit was included in the input of the amplifier to reduce the gain in higher frequenciesThe stable output SWR range increased with the RC filter to 2261 According to the simulations the series resistances caused about 046 dB gain loss and the RC filter again an additional 067 dB If the amplifier had to be unconditionally stable (K>1) in the frequency range of 01 GHz to 80 GHz the increase of series resistances to 9Ω would cause an additional 040 dB gain loss and more attenuation to the drive signal The total decrease of gain due to stabilization would then be 153 dB from maximum gain of 1136–983 dB In the implemented form the maximum simulated gain is 1023 dB
34 Input signal timing in a physically large transistor
During simulations there was a noticeable phase shift between extreme fingers of the wide transistor consisting of12918 transistors with a width of 50lm each This phase shift caused partial overlap between output pulses and decreased the drain efficiency At that time the input network was made of a ladderlike structure shown as an example in Fig9(a) The distance of the line between FETA and FET B is close to 1 mm which as a pure line delay would result in about 20 ps of delay But the delay difference was more than 80 ps and also the pulse width of the input signal was larger than predicted Since the transistors do not switch simultaneously they start to
load each other and consume more power The reason for increased delay and widened pulse width is the signal dependent gate capacitance that causes considerable amount of second harmonic distortion in the unterminated ladderlike input network in Fig9(a) where the signal paths are almost equal in lengthThis improved the timing behaviour and the input waveform phasing in the simulations was nearly the same Only the pulse width was still somewhat large The equal input routing increased the drain efficiency of the amplifier from55 to 68 The effects of gate capacitance together with additional solutions to timing problems have been published in [10]
4 Final circuit
The amplifier die sized 196mm ×362 mm (W×L) was glued directly to a 6mmthick aluminium heat sink The goldplated printed circuit board (PCB) containing output matching network and some of the gate biasing network was mounted onto the heat sink Next the chip was wire bonded and SMA connectors were added to the circuit The final circuit schematic is shown in Fig10 where the dashed line is used to separate the on and offchip components Lower left side in the figure is an LCmatching network which is followed by an RCsink circuit The RCcircuit increases the stability of the amplifier by providing a wideband loading at higher frequencies In the gate bias circuit upwards from the matching circuit is the parallel RLCcircuit that is a high impedance at the operating frequency while the offchip parallel RCcircuit provides additional bias resistance in the low frequencies thus increasing the stability of the amplifier On the right side of the transistor the tuned output resonator together with the offchip matching circuit is shown Drain supply voltage is directed through a long transmission line that is a high impedance at the operation frequency
The parallel gate RC bias circuit and output matching circuit were implemented on the PCB which simplified the implemented chip shown in Fig 11 Upper left box (a) is the LC input matching lower left box (b) is the RLC bias network and on the right of the bias is the box (c)containing the RCsink circuit The equal length input lines are shown in the box (d) where the added series resistors(5Ωeach) show as wide sections in between the equal length lines The transistor set is shown in box (e) and it consists of 12 transistors each of which contain 18 fingers with a width of 50lm each The saturation current of the transistor is about 4 A On the right from the transistor set there is the output path together with the parallel resonator in the box (f) Bonding pads are below (Gate bias) on the left (RF in) and up (RF out and drain bias) Two or three bondwires are used to minimize series resistance and inductance and also to maximize current capability of the wires
41 The implemented amplifier
The implemented amplifier is shown in Fig12togetherwith a picture of the chip layout The resonator structure on the right side of the layout is clearly visible in the actual chip The PCB had to be drilled open and the aluminium base plate machined for levelling the chip along the PCB surface This way the bondwires are kept as short
as possible The PCB contains the impedance transforming network required by the output of the amplifier Further the supply is provided through long line that has relatively high impedance at the fundamental and has low resistance atDC A part of the gate biasing network is also located in the PCB The total size of the PCB is 171 mm×376 mm(Width9Length)
5 Measured performance
51 Measurement setups
A single tone measurement was used to measure the amplifier output power and efficiency An IFR 2025 signal generator and a buffer amplifier from MiniCircuits provided the drive signal level of 25 dBm The output was measured with a Rohde & Schwarz ZVA 8 vector spectrum analyser (VSA)
The load pull measurements were performed with Focus Microwaves MPT 1820 tuners that were applied both to the input and output of the amplifier As a source was Rohde &Schwarz SMU 200A with a buffer amplifier The input power levels were from 15 to 25 dBm The RF input and output powers were measured with Anritsu ML2438Apower meter with dual input The harmonic content of the spectrum and oscillation spikes were measured with Rohde& Schwarz FSQ 40 VSA
52 Tuning of the amplifier
In the first measurements the amplifier did not meet the simulated response Measurements gave only 096 W of output power at 1575 MHz when the simulated figures were 34 W of output power and drain efficiency of 70all at supply voltage of 55 V Our suspicion directed towards a scribe line that passed very close to the output resonator structure and possibly could couple the output to the input of the amplifier The scribe line was cut with an UVlaser but this had no effect to the frequency responseThe measured DC current of the amplifier was considerably higher than simulated suggesting that the load impedance of the switching stage was too low The impedance seen at the drain was increased by replacing a pair of 27 pF highQ ceramic capacitors (Amplifier A inTable1) in the external output matching network with one 29 pF capacitor (Amplifier B in Table1) This modification increased the output power to 2 W and the drain efficiency to 56 at the frequency of
1625 MHz The output power and efficiency in the frequency range of15–17 GHz is shown in Fig13 The output power is maintained within 053 dB in the desired frequency range(16265–16605 MHz) as shown in Fig 13 Within that same frequency band the drain efficiency stays above53 while the highest efficiency 56 is achieved at1626 MHz
By adjusting the supply voltage the efficiency of the amplifier can be increased even more which can be seen from Fig14 Drain efficiency increases steadily when supply is lowered At a supply voltage of 25 V and frequency of 1625 MHz the amplifier has a drain efficiency of 65 This implies that the amplifier can maintain an efficient operation also when used in an envelope elimination and restoration (EER) system The high peaks in at lowest supply voltages in Fig 14are caused by drive signal feedthrough that sums into the output signal
53 Load pull measurements
Measurements were performed with load pull system at16 GHz spot frequency to several modified amplifiers The differences between the amplifiers are shown in Table1In the next chapters we will mainly concentrate on amplifiers C and D for reasons that will be apparent later on Let us now discuss the amplifier C which is very similar to amplifier B measured earlier Tuners of the load pull system were connected to the outputs and inputs of the amplifier C The load tuning of fundamental second harmonic and third harmonic resulted in about 24 W of output power (338 dBm) while maintaining about 574 drainefficiency at this peak power spot
The fundamental load impedance in terms of power was at slightly higher impedance than the optimum drain efficiency point as shown in Fig15 where the 1 dB output power points (triangles) and5 unit efficiency points(circles) are shown The peak efficiency point in the figure is (a) (586) and peak power is (b) (339 dBm) The optimum efficiency area is rather large
Both of the load harmonics were even more relaxed and differences for example in output power had to be measured in tenths of decibels rather than in
decibels Furtherthe efficiency differences were measured in one or two percentage units instead of five to ten As an example the third harmonic optimum output points within 02 dB from maximum (triangles) and efficiency points within 2 units from maximum (circles) are shown in Fig 16 As it can beseen the third harmonic impedance is not as critical as the fundamental tone The optimum efficiency is marked with(a) and maximum output power is marked with (b) It should be noted that the adjustment of the third harmonic did not increase output power on the absolute scale nor the drain efficiency The peak output power value remained within 02 dB of the peak value of the fundamental load pull and the drain efficiency rose from 586 only to 598shown at the Smith chart point (a) in Fig16
The insensitivity of the amplifier to harmonic tuning is caused by the long drain bias line that is low impedance at the second harmonic and the low pass matching network at the output that attenuates the third harmonic
54 Source pull measurements
The source pull of the fundamental impedance did increase the output power and efficiency of amplifier C slightly The optimum drain efficiency (circles) and output power points(triangles) (a) and (b) respectively are shown Fig 17 The power points are within the limits of 02 dB and efficiency within a difference of 2 units The amplifier efficiency rose with the fundamental source tuning to 621 (point a)and the output to about 25 W (341 dBm point b) Harmonic source pull measurements showed that the harmonic impedances were not as critical as the fundamental This is due to the low pass input matching and the wideband RCsink circuit The RCsink circuit lowers the calculated magnitude of the impedance especially at high frequenciesas shown in Fig18(b) This has an effect to both second and third harmonic impedances The magnitude of the impedance without the RCsink is shown as a reference in Fig18(a) In both cases the input matching circuits were not included in the calculations
55 Stability of the amplifier
At first the amplifier A did show some unstable behaviour due to supply voltage modulation caused by insufficient bias decoupling at the drain The instability appeared at low input power levels as noise sidebands that lied on both sides of fundamental frequency When input power was lowered further on the amplifier did break into full scale oscillation As a cure the supply impedance was lowered by a large number of decoupling capacitors (4 ×470 pF)added to the drain In an EER application the supply modulator will provide low enough impedance at the drain
When the load pull was done to the amplifiers A C and D a spurious oscillation detection was applied at a level of50 dBc With this setup we were able to compare the sensitivity of different amplifiers to oscillations We found out that the RCsink circuit used in amplifiers A and C indeed improved stability especially in the low input power levels Data used for comparison was measured from amplifier D where the RCsink was cut using an ultraviolet laser The oscillation points of the fundamental impedance load pull with a low 15 dBm input power are shown in
Fig19
The oscillation sidebands detected are1701 and 1489 MHz If we compare this result to amplifier A the amount of found oscillation points is considerably smaller and the location of them is rather tightly spaced in the low impedance area as shown in Fig 20 The oscillation frequency in this case is 1568 MHz The amplifier A and amplifier
D had a different frequency for the modulating spurious components Without the damping circuit the modulating spurious was ca±100 MHz while with the damper the modulation appeared at about±30 MHz The probable reason for this lies in different drain bypassing as the amplifier D had less supply capacitance (4×470 pF less) The effect of this was studied by simulating from input to load transmission (S21) in the drain bias and matching network The circuit from amplifier D shows resonance at around 93 MHz as shown in Fig 21(a) while in the amplifier A the drain resonance is at 27 MHz frequency as shown in Fig21(b) As a reference a measured spectrum of amplifier A’s output is shown in Fig22 where the markers one and four are at±33
MHz distance from the fundamental frequency The input power in this case is15 dBm and fundamental load impedance is at one of the found oscillation impedances(Г0370Ø1653)The increase of chip decoupling capacitors (4×470 pF) in the case of amplifier A did lower the resonance from around100 MHz into 30 MHz region Inside the±30 MHz band there are also other oscillation tones which resemble a quasiperiodic solution and a chaos spectrum combinedExamples of quasiperiodic and chaos spectrums are shown for example in [11] An interesting point of the resonance seen was that the large electrolytic capacitors applied to the bias supply did not attenuate the about 30 MHz resonancedue to its high inductance
56 Additional findings
Switching amplifiers are dependent on sufficient amount of gate drive and
variations in the drive signal affect quickly the performance of the amplifier In our case small variations in transistor pinchoff voltage resulted in 2–3 dB differences in gain between the amplifiers when bias voltage was kept constant Such clear differences could beseen in vector network analyser measurements with a 0 dBm input drive More constant results could be derived by adjusting the small drain bias currents to equal when no drive signal was applied Now the measurements of gain were matched within 08 dB
6 Summary
A tuned RF power amplifier has been designed for operation in a frequency band of 16–17 GHz The amplifier was designed empirically to have nonoverlapping drain voltage and current pulses and the required resonant circuit was implemented onchip A new position of the DCblocking capacitor genereted a resonator trap that stabilizes the amplifier below the desired band and a gate RCsink circuit was used to stabilize the amplifier at higher frequencies Further equal length input lines were implemented to equalize the timing of gate signals
The stability of the amplifier was evaluated through simulations of large signal Sparameters and stability circles Additional resistances together with an RCsink circuit had to be applied to keep the stable output SWR range at more than 2261 The amplifier was implemented onto a GaAs substrate with depletion mode high electron mobility transistors (FETs) The implemented amplifier delivers 2 W of output power while maintaining 56 drain efficiency The frequency response is within 053 dB at a frequency band of 16265–16605 MHz while the drain efficiency stays above 53 in this desired band
The amplifier was also measured with a load pull system at a spot frequency of 16 GHz With the help of tuners the amplifier achieved about 25 W of output power and 62efficiency Load pull also revealed the amplifier’s sensitivity to oscillations at small drive levels It was found out that the output matching network has a lowfrequency resonance that might contribute to the unstable behaviourThe implemented gate sink was verified to stabilize the circuit
It might be a beneficial idea to design an input LCtrap circuit tuned to the second harmonic since there is second harmonic content at the input which widens the input waveform in the time domain creating problems in terms of efficiency and power Further increasing the third harmonic content could make the input waveform more squarelike which is a desired feature in switching amplifiers
Acknowledgements： This work has been supported by The Academy of Finland Infotech Oulu Graduate School TriQuint Semiconductor Inc Nokia Foundation Tauno Tonning FoundationUlla Tuominen Foundation and The foundation of Riitta and Jorma J Takanen My special thanks to the personnel of the Department of Electronics and Telecommunications in the Norwegian University of Science and Technology (NTNU) and to the personnel of the Micro and Nanotechnology Centre in the University of Oulu
References
1 Cripps S C (2006)RF power amplifiers for wireless communications (2 edn) 685 Canton Street Norwood MA 02062Artech House Inc
2 Raab F (1977) Idealized operation of the class e tuned power amplifierCircuits and Systems IEEE Transactions on 24(12)725–735
3 Sokal N O & Sokal A D (1975) Class e–a new class of high efficiency tuned singleended switching power amplifiersIEEE Journal of SolidState Circuits 10(3) 168–176
4 Mury T & Fusco V (2005) Serieslparalleltuned classepower amplifier analysis InProc European microwave conference(Vol 1 p 4) doi101109EUMC20051608890
5 Tayrani R (2007) A spectrally pure 50 w high pae (6–12 ghz)gan monolithic class e power amplifier for advanced tr modulesIn Proc IEEE radio frequency integrated circuits (RFIC) symposium(pp 581–584) doi101109RFIC2007380951
6 Hietakangas S Rautio T & Rahkonen T (2006) 1 ghz class erf power amplifier for a polar transmitter In Proc 24th norchipconference(pp 5–9) doi101109NORCHP2006329232
7 Hietakangas S Rautio T & Rahkonen T (2008) One ghz class e rf power amplifier for a polar transmitterAnalog Integrated Circuits and Signal Processing An International Journal54(2) 85–94 doi101007s104700079109x
8 Triquint Semiconductor Inc (2007)TQPED 05 um ED pHEMT foundry service (22 edn) httpwwwtriquintcomprodservfoundrydocsTQPEDv2_2pdf
9 Kazimierczuk M & Tabisz W (1989) Class ce highefficiency tuned power amplifier Circuits and Systems IEEE Transactions on 36(3) 421–428 doi1011093117589
10 Hietakangas S Typpo J & Rahkonen T (2008) Effects of input routing in switched rf amplifiers In Proc workshop on integrated nonlinear microwave and millimetrewave circuits INMMIC 2008(pp 35–38) doi101109INMMIC20084745708
11 Suarez A Jeon S & Rutledge D (2006) Stability analysis andstabilization of power amplifiers IEEE Microwave Magazine7(5) 51–65 doi101109MWM2006247915
Simo Hietakangaswas born in Alaha¨rma ¨ Finland in 1980 He received the MSc degree in Electrical Engineering from the University of Oulu Oulu Finland in 2005 and is currently working toward the PhDdegree at the University of Oulu His technical interests lie in the field of analysis and modeling of switching RF power amplifiers
Jukka Typpo¨was born in OuluFinland in 1963 He received his MSc degree in University of Oulu in 1992 and his PhDdegree in Norwegian University of Science and Technology in2003 Currently he works as a research fellow at Norwegian University of Science and Technology Department of Electronics and Telecommunications His current research topic is integrated RF power amplifiers
Timo Rahkonenwas born inJyva ¨skyla ¨ Finland in 1962 He received the Diploma EngineerLicentiate and Doctor of Technology degrees from the University of Oulu Oulu Finlandin 1986 1991 and 1994respectively He is currently a Professor of circuit theory and circuit design with the University of Oulu where he conducts research on linearization and errorcorrection techniques for RF power amplifiers and
AD and DA converters
16GHZ2W集成式调谐射频式接收功率放器设计
摘：篇文种指定运行行频率1626516605MHZ范围国际海事卫星集成调谐功率放器描述放器基拓扑结构行优化逆E类放器修改类放器通新位置安装直流隔离电容通调整电容尺寸提高低预期波段频率稳定性外新安放位置减少排水负载损失电路中高电流宽电感宽度芯片谐振器高Q值手指电容必该放器实现砷化镓（GaAs）集成电路（IC）交付2 W输出功率漏极效率约 56％测量包括信号源负载达进步改善该放器性输入驱动电进行时调查稳定性
关键词：逆E级功率放器激振荡偏置网络
1介绍
天高功率通信系统传统线性放器性低效率限制事实推动更高效放器研究兴趣E级[13]逆E级[4]外较高输出功率需求意味着更高峰值电流电压漏极集电极电路创建求高晶体两击穿值单片微波集成电路（MMIC）源电路限导电性限电容应付热效果通仔细设计MMIC达化外晶体新兴技术似承受更电流密度峰值电压[5]设计高功率器件时技术选择变越越重
文目显示开关高功率射频（RF）功率放器（PA）具集成输出脉整形设计验第二章中介绍E级逆E级操作重新审视两种拓扑结构间差异第三章介绍输入输出电路稳定电路设计提供提示关指晶体输入端减少时差方式第四章出终原理实现芯片片第五章中实测性通两基单音测量设备现代化负载拉移系统采功调谐器（MPT）进行报告部分提供关稳定电路问题文章讨摘
2E级反E级放器
E级逆E级视开关放器理想情况两者晶体驱动开关闭该开关动作产生系列电压电流脉输出脉相移会彼重叠理想非重叠导致晶体具100％漏极效率操作典E类漏极波形化电源电流电压DC值展示图1实线化漏极电流波形虚线化漏极电压E类佳操作求零电压开关（ZVS）中漏极电压衍生物变零晶体导通前进行逆E类波形已交换位置便图1中实线波形漏极电压虚线漏电流佳操作改变零电流开关（ZCS）中电流衍生物利变零晶体进入非导通阶段前逆E级相典实现优点漏极峰值电压传统E级较低输出电路中电感值较MMIC芯片实现节省面积通常更电器串联电阻（ESR）[4]外接收串联电感作振电路部分性寄生电抗引起阻尼振排出波形[67]优势选择逆E类拓扑结构作研究出发点原然调谐执行传统逆E级然类似脉操作
3调谐功率放器设计
31砷化镓IC工艺
IC工艺TriQuint半导体公司伪形态高电子迁移率晶体(pHEMT) 命名TQPED工艺该工艺采增强型耗型场效应两晶体（FET）具05lm长光学光刻门例子中耗型晶体耗型晶体具27千兆赫渡频率（f t）漏极 栅极击穿电压1605 V08V晶体模型中标称夹断点TOM3 FET模型工业中特点：镍铬合金（镍铬）电阻精度宗高值电阻高价值金属 绝缘体 金属（MIM）电容12层厚度全球金属层[8]
32振器设计
图2中原始逆E级设计中调谐拓扑结构存差图3示阻断电容器Cs位置
图2示原始安装提供隔直流分两方：输出（负载） 更重会阻止直接通电感Lp直流电流路径情况中阻塞电容器谐振电路方图3示中铯妨碍直流电流流电感Lp输出（负载）直接方法基电流流输出会传递阻塞隔电容器直流阻塞电容器现做更情况中100 pF减少低50 pF意味着芯片面积节省作辅助效果够调整稳定陷阱需频率（第三章32）时保持良放器性直流阻隔设计现稍微容易峰值电流流入阻断分支较外漏极负载间ESR更Cs元器件中基波电流振幅分
122 A图3中出联谐振器结构总峰值电流
传统逆E类标注[ 4 ] 数16 GHz功率输出 3 W导致较芯片面积较高Q 10总电容较（ 635 PF） 高峰值电流（约6 A ）电感变巨获合理芯片元件值设计逐渐[4]中设计程转较低负载电阻Q值增加振频率结束提供整齐重叠标注电流电压脉合理尺寸源器件终更接C级E基负荷原逆E类模拟终元件值[ 9 ]分立元件模型片外低通阻抗匹配网络50Ω导致尺寸：阻性负载4Ω CTOT 30 pF电感 LP 022 NHL终设计忽略铯降低50 pF影响整体性调整稳定低载波陷波面图 8 示带开关晶体（具18×50μm05μm手指电容12联晶体）估计56 W输出功率72％漏极效率总仿真结果现面挑战现维护良输出功率效率时取代（PDK）制程设计套件（PDK）组件代理想电路元件时增加稳定电路拓扑结构设计问题电感物理设计降低Q值电流幅度然高（42 A峰值）感应器概需200lm宽金属线保持34弯度电感器中心开理04 nH总电容Q值进步减少点减少电阻损耗总电容分成12联高Q电容器谐振器结构绘制布局导入25D场模拟S参数进行模拟离散模拟原型进行较S参数模拟较阻抗数卸载相位幅度显示图45分布式谐振器相位幅值数两数字标记虚线谐振器相位幅度遵循相曲线完整放器进行模拟漏极效率约70％输出功率概34 W输出功率减少解释寄生电阻稳定电路导致漏极效率出意料降低Q验输出电路设计方式仿真实现分布式谐振器图6示
33 稳定化放器
该放器显示种信号S参数（LSSP）模拟时稳定倾终稳定必须通LSSP基础稳定电路里进行评估条件稳定（K>1）没重损失实现稳定电路画整055 GHz频率范围次仿真种稳定电路必须补偿振铃性首先分立电容器Cs调谐50 pF直生成输出谐振器陷约12千兆赫频率助面通罗莱特K系数图7示频率茅屋频率达稳定 50 pF值选定输出功率较损失良稳定性电容器Cs调谐影响示图8中电容器调谐30〜70 pF范围
进步说5Ω串联电阻添加图9（b）示3栅极线保持放器稳定范围461输出驻波（SWR）外宽频带RC宿电路包括放器输入端减少较高频率增益稳定输出SWR范围增益增加RC滤波器2261根模拟串联电阻引起约046 dB增益损耗RC滤波器额外067分贝果放器必须条件稳定（K>1）01千兆赫80千兆赫频率范围串联电阻增加9Ω导致该驱动信号额外040分贝增益损失更衰减1136983分贝增益然增益稳定总跌幅降153分贝执行仿真程中模拟增益1023分贝
34体积较晶体输入时钟信号
仿真期间广泛晶体组成12918晶体50lm宽度极端手指间明显相移种相移引起部分重叠输出脉间降低漏极效率时输入网络作出示图9（a）例子阶梯状结构 FETA场效应B间线距离接1毫米作纯粹线延迟导致约20 ps延迟延迟差超80 ps样输入信号脉宽度预测晶体时切换开始加载方消耗较电究原增加延迟展宽脉宽度信号赖栅极电容导致图9（a）未结束阶梯状输入网络相数量二次谐波失真中信号路径相等长度改进时序行输入波形相位模拟相脉宽度点相等输入路增加放器55漏极效率68％栅极电容附加解决方案时序
问题影响已发表[10]
4终电路
该放器模具尺寸196毫米× 362毫米（宽×长）直接粘6mm厚铝制散热片含输出匹配网络栅极偏置网络镀金印刷电路板（PCB）安装散热器未芯片键合线SMA连接器添加电路中终电路示意图示图10 中虚线分隔芯片外组件左侧图中RC宿电路LC匹配网络该RC电路提供宽带装载较高频率增加放器稳定性栅极偏置电路述匹配电路联RLC电路工作频率高阻抗片联RC电路提供额外偏置电阻低频率增加稳定性放器右侧晶体该调谐输出谐振器芯片外匹配电路起示出漏极供电电压通长传输线操作频率高阻抗定
行栅极RC偏置电路输出匹配电路中电路板简化实施芯片实现图 11示左框（a）LC输入匹配左框（b）RLC偏置网络偏置右侧包含RC宿电路方块（c）示长度相等输入线显示框中（d）中中添加串联电阻（5Ωeach）显示宽部分中相等长度行间晶体集显示话框（E）12晶体
包含18手指50lm宽度晶体饱电流约4 A晶体集合右边输出路径连框中（f）该联谐振器焊盘低（门偏置）左侧（RF中）高达（RF输出漏极偏置）两三接合线量减少串联电阻电感时限度提高导线输送电流力
41 实现放器放器
实现放器图12示芯片布局图起实际芯片右侧布置谐振器结构清晰见PCB必须钻开铝基板加工PCB表面整芯片样接合线保持短印刷电路板包含放器输出需阻抗变换网络外电源具相高阻抗基波具低电阻ATDC长线路提供门偏置网络部分位PCB PCB总171㎜×376毫米
5测试性
51测试计划
单音测量测量放器输出功率效率IFR2025信号发生器微型电路缓放器提供25 dBm驱动信号电输出罗德施瓦茨ZVA8矢量频谱分析仪（VSA）测量
负载牵引测量进行该均施加放器输入输出聚焦微波MPT1820调谐器作源罗德施瓦茨公司SMU200A带缓放器输入功
率水分15〜25 dBm RF输入输出功率测量安立ML2438A功率测定仪双输入频谱振荡尖峰谐波含量测定Rohde＆Schwarz公司FSQ40 VSA
52调谐放器
述第测量放器符合仿真响应测量096 W输出功率1575 MHz时仿真数字分34 W输出功率漏极效率70％电压源55 V怀疑电源电压指该传递非常接输出划线谐振器结构耦合输出放器输入端划线切割紫外线激光必须测量放器直流电流频率相应没结果模拟高表明开关级负载阻抗太低漏阻抗增加更换27 pF高Q值陶瓷电容（放器A表1）外部输出网络29 pF电容匹配（放器B表1）该变形增输出功率2瓦漏极效率56％625兆赫频率输出功率频率范围1517 GHz效率示图13输出功率保持053分贝需频率范围（1626516605兆赫）图13示保持相频带漏极效率保持53％高效率56％达1626兆赫
通调节供电电压放器效率进步增加图14中出供电电压降低漏极效率稳步升25 V1625 MHz频率电源电压时放器具65％漏极效率意味着该放器保持高效操作包络消恢复（EER）系统中时峰值电压低电源电压图 14根输出信号驱动信号馈通
53负载迁移测试
测量负载拉移系统16GHz频率点进行修改放器放器间差异显示表接章节中集中放器CD原显易见现讨放器C非常相似放器B早期测量负载拉移系统调谐器连接放器C输出输入基波二次谐波三次谐波负载调谐导致约24W输出功率（338dBm）时保持约574％效率峰值功率点
电力方面基负载阻抗佳漏极效率点稍高阻抗图15示中1分贝输出功率点（三角形）5％单元效率点（圆圈）示出图中峰值效率点（a）（586％）峰值功率（B）（339 dBm）佳效率区域相
两负载谐波甚更放松输出功率实施例区测定分贝十分分贝外效率差异测定两百分单位代五十作例子第三谐波佳输出02分贝2％单位（圆圈）（三角形）效率分点显示图16见三次谐波阻抗关重基音佳效率标（a）输出功率标（b）示应指出三次谐波调整没增加绝尺度漏极效率输出功率峰值输出功率值保持基负载牵引漏极效率峰值
02dB仅仅升586％598％图16史密斯圆图（a）点示
放器谐波调谐敏感性长漏极偏置线第二谐波低阻抗低通匹配网络该衰减三次谐波输出引起
54 元迁移测量
根阻抗源拉提高输出功率放器Ç稍微效率佳漏极效率（圆圈）输出功率点（三角形） （ a）（ b）中分示出图 17 电源点范围2 ％单位差02分贝效率限制该放器效率提高根源泉调整621 ％ （点）输出约25瓦（ 341 dBm时 b点） 谐波源拉测量结果表明谐波阻抗样重基础低通输入匹配宽带RC宿电路RC 宿电路降低阻抗尤高频率计算幅度图18（ b）示具效果二次三次谐波阻抗未RC漏极阻抗图18中（ a）示两种情况输入匹配电路包括计算中
55放器稳定性
起初放器A确实显示稳定行引起足耦偏置漏极电压调制稳定出现低输入功率水噪声边带骗基频两侧输入功率进步调时放器入全面振荡作治疗电源阻抗量耦电容（4×470 PF）降低加漏效应中电源调制器提供足够低阻抗漏级
负载拉做放器ACD中寄生振荡检测50 dBc水施加采种设置够放器灵敏度进行较振荡发现RC宿电路放器AC确实改善稳定性尤低输入功率水较数放器D中RC漏极紫外线激光切割测定低15 dBm输入功率基阻抗负载牵引振荡点示图19
振荡边带检测are17011489兆赫果较该结果放器A发现振荡点数量相位置相紧密间隔低阻抗区域中图示 20种情况振荡频率1568兆赫放器A放器D调制虚拟原件：阻尼电路虚拟调制频率约±100兆赫然存阻尼时调制出现约±30兆赫现象原漏级旁路放器D较少供应电容（4×470 pF更少）通输入加载传输（S21）中漏极偏压匹配网络研究现象影响放器D中电路显示出谐振约93兆赫时反应图21（a）放器A漏极振27 MHz频率图21（b）示示作参考放器A输出测定光谱示图22中标记物1四正处基频±33兆赫距离该图中种情况输入功率15 dBm基负载阻抗发现振荡阻抗（Г0370O 1653）芯片耦电容（4×470 pF）放器A情况增加降低约100兆赫30兆赫区域做振时反应±30 MHz频段类似准周期解决方案准周期混沌光谱组合例准周期混沌光谱[11]显示振趣问题高电感系数施加偏置供应型电解电容器没减弱约30 MHz振
56额外发现
开关放器赖栅极驱动器足够数量种样驱动信号快速影响放器性例子中晶体夹断电压微变化导致23分贝时增益差放器间时电压保持恒定种明显差异发现矢量网络分析仪测量0 dBm输入驱动时更加恒定结果推断通调节微漏极偏置电流相等时没驱动信号施加现增益测量结果08分贝匹配
6总结
调谐射频（RF）功率放器已设计1617 GHz范围频带操作放器根验设计具非重叠漏极电压电流脉求谐振电路已芯片应阻隔直流电容器新位置会产生谐振陷阱谐振陷阱放器稳定低需频带范围栅极
RC宿电路稳定放器工作较高频率外长度相等输入线实施时钟门信号
放器稳定性通信号S参数稳定圆模拟评价附加电阻RC宿电路起施加保持输出SWR超2261稳定放器应GaAs衬底具耗型高电子迁移率晶体（FET已应放器提供输出功率2瓦时保持56％漏极效率频率响应053分贝频带1626516605兆赫范围漏极效率保持高53％期频带
16 GHz频率放器测量负载牵引系统调谐器放器帮助实现输出功率约25 W62％效率负载牵拉驱动电时放器灵敏度振荡程度关发现输出匹配网络具导致稳定表现低频振实行门沉验证稳定电路
益想法设计调谐第二谐波输入LC陷波电路中存该加宽输入波形时域效率功率方面产生问题输入第二谐波时进步增加第三谐波含量输入波形变更加趋方形开关放器希特征
感谢：篇文 The Academy of Finland Infotech Oulu Graduate School TriQuint Semiconductor Inc Nokia Foundation Tauno Tonning FoundationUlla Tuominen Foundation and The foundation of Riitta and Jorma J Takanen支持 the Department of Electronics and Telecommunications in the Norwegian University of Science and Technology (NTNU) and to the personnel of the Micro and Nanotechnology Centre in the University of Oulu表示衷感谢
参考文献
Cripps S C (2006)RF power amplifiers for wireless communications (2 edn) 685 Canton Street Norwood MA 02062Artech House Inc
2 Raab F (1977) Idealized operation of the class e tuned power amplifierCircuits and Systems IEEE Transactions on 24(12)725–735
3 Sokal N O & Sokal A D (1975) Class e–a new class of high efficiency tuned singleended switching power amplifiersIEEE Journal of SolidState Circuits 10(3) 168–176
4 Mury T & Fusco V (2005) Serieslparalleltuned classepower amplifier analysis InProc European microwave conference(Vol 1 p 4) doi101109EUMC20051608890
5 Tayrani R (2007) A spectrally pure 50 w high pae (6–12 ghz)gan monolithic class e power amplifier for advanced tr modulesIn Proc IEEE radio frequency integrated circuits (RFIC) symposium(pp 581–584) doi101109RFIC2007380951
6 Hietakangas S Rautio T & Rahkonen T (2006) 1 ghz class erf power amplifier for a polar transmitter In Proc 24th norchipconference(pp 5–9) doi101109NORCHP2006329232
7 Hietakangas S Rautio T & Rahkonen T (2008) One ghz class e rf power amplifier for a polar transmitterAnalog Integrated Circuits and Signal Processing An International Journal54(2) 85–94 doi101007s104700079109x
8 Triquint Semiconductor Inc (2007)TQPED 05 um ED pHEMT foundry service (22 edn) httpwwwtriquintcomprodservfoundrydocsTQPEDv2_2pdf
9 Kazimierczuk M & Tabisz W (1989) Class ce highefficiency tuned power amplifier Circuits and Systems IEEE Transactions on 36(3) 421–428 doi1011093117589
10 Hietakangas S Typpo J & Rahkonen T (2008) Effects of input routing in switched rf amplifiers In Proc workshop on integrated nonlinear microwave and millimetrewave circuits INMMIC 2008(pp 35–38) doi101109INMMIC20084745708
11 Suarez A Jeon S & Rutledge D (2006) Stability analysis andstabilization of power amplifiers IEEE Microwave Magazine7(5) 51–65 doi101109MWM2006247915
Simo Hietakangaswas born in Alaha¨rma ¨ Finland in 1980 He received the MSc degree in Electrical Engineering from the University of Oulu Oulu Finland in 2005 and is currently working toward the PhDdegree at the University of Oulu His technical interests lie in the field of analysis and modeling of switching RF power amplifiers
Jukka Typpo¨was born in OuluFinland in 1963 He received his MSc degree in University of Oulu in 1992 and his PhDdegree in Norwegian University of Science and Technology in2003 Currently he works as a research fellow at Norwegian University of Science and Technology Department of Electronics and Telecommunications His current research topic is integrated RF power amplifiers
Timo Rahkonenwas born inJyva ¨skyla ¨ Finland in 1962 He received the Diploma EngineerLicentiate and Doctor of Technology degrees from the University of Oulu Oulu Finlandin 1986 1991 and 1994respectively He is currently a Professor of circuit theory and circuit design with the University of Oulu where he conducts research on linearization and errorcorrection techniques for RF power amplifiers and AD and DA converters
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Abstract： This paper describes the design of an integrated tuned power amplifier specified to operate at Inmarsat satellite uplink frequencies from 16265 to 16605 MHzThe basic topology of the amplifier lies on the parallel tuned inverse class E amplifier that is modified by placing the DCblocking capacitor into a new position and by adjusting the size of the capacitor to improve stability below the desired band Further the new positioning reduces losses between drain and load The high currents flowing in the circuit made it necessary to use wide inductor width and highQ finger capacitors in the onchip resonator The amplifier was implemented as a Gallium Arsenide (GaAs) integrated circuit (IC) that delivered 2 W of output power while the drain efficiency was ca 56Measurements included source and load pulls to further improve the performance of the amplifier and to investigate the stability at small input drive levels
Keywords Inverse class E•Power amplifierSelfoscillation• Bias network
1 Introduction
The usability of traditional linear amplifiers in today’s high power communications systems is limited due to their low efficiency This fact has driven the interest of research towards more efficient amplifiers such as class E [1–3] and inverse class E [4] Also the demand of higher output power means higher peak currents and voltages in the drain or collector circuits This creates high requirements for both maximum breakdown values of the transistor and to the passive circuitry of the monolithic microwave integrated circuit (MMIC) The effect of limited conductivity and limited capability to cope with heat can be minimized through careful design of MMIC Further emerging transistor technologies seem to withstand larger current densities and peak voltages [5] and therefore the choice of technology is increasingly important when designing high power devices
The aim of this paper is to show experiences related to the design of switching high power radio frequency(RF) amplifiers (PA) with integrated output pulse shaping In the second chapter the introduction to class E and inverse class E operation is revisited and the differences between the two topologies are reviewedThe third chapter describes the design of the input and output circuitry stabilizing circuits and provides some tips to minimize timing differences at the input of a multifinger transistor The fourth chapter shows the final schematic and a photo of the implemented chip The measured performance is reported in chapter five by using both basic single tone measurement equipment and a modern load pull system using multipurpose tuners(MPT) The last section provides a summary of the article and discussion of the issues related to stabilizing circuits
2 Class E and inverse class E amplifiers
Class E and inverse class E are regarded as switching amplifiers Ideally in both of them the transistor is driven either on or off and this switching operation
produces a series of voltage and current pulses to the output These pulses are phase shifted and therefore do not overlap with each other Ideal nonoverlap causes the transistor to operate with drain efficiency of 100
Classical class E drain waveforms normalized to DC values of supply current and voltage are shown in Fig1The solid line is normalized drain current waveform and the dashed line is normalized drain voltage The requirement for optimal operation in class E is zero voltage switching (ZVS) where the drain voltage and its derivative goes to zero just before the transistor starts to conduct In inverse class E the waveforms have swapped places so that the solid line waveform in Fig1 is the drain voltage and the dashed line is the drain current The optimal operation is also changed to zerocurrent switching (ZCS) where the current and its derivative goes smoothly to zero before the transistor enters nonconducting phase Advantages of inverse class E over classical realization are that the drain peak voltages are lower than in classical class E and the inductance values in the output circuitry are smaller which can save area in a MMIC chip implementation and can usually give smaller electrical series resistance (ESR) [4] Also the possibility to accommondate series inductance as a part of resonating circuitry is useful since the parasitic reactances can cause undamped resonances to drain waveforms [6 7] These advantages were the reasons for choosing inverse class E topology as a starting point for our investigation However the tuned implementation is not traditional inverse class E although it has similar pulsed operation
3 Design of tuned power amplifier
31 GaAs IC process
The IC process used is a Triquint Semiconductor’s pseudomorphic high electron mobility transistor (pHEMT) process named TQPED The process utilizes both enhancement and depletion mode field effect transistors (FETs) with 05lm length optical lithography gates but in our case we used only depletion mode transistors The available depletion mode transistors have a transition frequency (Ft) of 27 GHz draingate breakdown voltage of15 V and nominal pinchoff point of08 V Transistors models used are TOM3 FET models There are several other features in the process nichrome (NiCr) resistors for precision and bulk for high value resistors high value Metal–Insulator–Metal (MIM) capacitors 1 local and 2thick global metal
layers [8]
32 Design of the resonator
The difference between the original inverse class E in Fig2and the final tuned topology used in our designshown in Fig3 is the location of blocking capacitor Cs
The original placing in Fig2provides the DCblocking to two directions to the output (load) and more important it blocks the direct DCcurrent path through Lp to groundIn our case the blocking capacitor is underneath the resonating circuit as shown in Fig3 where the Cs obstructs the flow of DCcurrent through Lp to ground but not to the output (load) There is a direct way for fundamental current to flow to the output without passing any blocking capacitor The DC blocking capacitor can now be made significantly smaller In our case the reduction was from100 pF to less than 50 pF which means savings in chip area and as a secondary effect the ability to tune a stabilizing trap to wanted frequency (more in chapter 32) while maintaining good amplifier performance The design of the DCblock is now also slightly easier since peak current flowing into the blocking branch is smaller Furthermorethe ESR between drain and load is smaller The fundamental current amplitudes in components Cs andLwere12 and 2 A respectively The total peak currents in the parallel resonator structure can be seen in Fig3
The traditional inverse class E dimensioning [4] for16 GHz and Pout3 W results in large chip area as due to high Q 10 the capacitor Ctot is large (635 pF) and—due to high peak currents (ca 6 A)—the inductor gets physically huge To get reasonable onchip component values the design was gradually deviated from the design procedure in [4] by shifting it towards lower load resistance and Q value and increasing the resonance frequency This ended up in a dimensioning that provides clean nonoverlapping current and voltage pulses reasonable size passives but which is eventually closer to class C–E fundamental load [9] than to original inverse class E The final component values of the simulation with discrete component models and an offchip lowpass impedance matching network to 50Ω resulted in the following dimensioningresistive load 4ΩCtot 30 pFLp022 nHand L so small it could be omitted from the final designCs could be reduced down to 50 pF without affecting the overall performance and it can be used to tune a stabilizing below thecarrier notch as shown later in Fig 8 The overall simulation results with a large switching
transistor (12parallel transistors with 18×50µm05µm fingers) estimated 56 W output power with 72 drain efficiency The challenge was now to maintain as good output power and efficiency while replacing the ideal circuit components with process design kit (PDK) components and while adding some stabilizing circuits to the topologyNext design problem came with the physical design of the inductor Despite the lowered Q value the current amplitude was still so high (42 A peak) that ca 200lmwide metal line was needed for the inductor and to keep the center of the 34turn inductor open it could not be made physically smaller than 04 nH Hence the capacitance Ctot and Q value were further reduced a bit and to reduce resistive losses the capacitance Ctot was split into 12parallel highQ capacitors The drawn layout of the resonator structure was imported into 25D field simulator and Sparameters were simulated and compared with those of the discrete simulation prototype The unloaded phase and magnitude of the impedance data for comparisons from Sparameter simulations are shown in Figs4and5 The phase and magnitude data of a distributed resonator is marked with a dashed line in both figures The phases and magnitudes of the resonators follow almost the same lineWhen the complete amplifier was simulated the drain efficiency was about 70 and output power was about34 W The reduction in output power may be explained by parasitic resistances and by the addition of stabilizing circuits The drain efficiency is surprisingly good despite the somewhat lowered Q and empirical output circuit designThe simulated and implemented distributed resonator is shown in Fig6
33 Stabilizing the amplifier
The amplifier showed a tendency of instability during largesignal Sparameter (LSSP) simulations In the endstability had to be evaluated through LSSPbased stability circles since unconditional stability (K>1) could not be achieved without heavy losses Stability circles were drawn throughout a frequency range of 05–5 GHz After several simulations a variety of stabilizing circuits had to be used to compensate ringing behaviourFirst the discrete capacitor Cs was tuned to 50 pF to generate a trap in the output resonator at about 12 GHz frequency This helped in achieving stability at frequencies below the frequency bandas shown by Rollett’s Kfactor in Fig7 The 50 pF value was chosen for both small degradation in output power and for good stability performance The effect of tuning of the capacitor Cs is shown in Fig 8 where the capacitor is tuned from 30 to 70 pF
Further 5Ωof series resistance was added to three gate lines as shown in Fig 9(b) to keep the amplifier stable with output standing wave ratio (SWR) range of 461 Also a wideband RCsink circuit was included in the input of the amplifier to reduce the gain in higher frequenciesThe stable output SWR range increased with the RC filter to 2261 According to the simulations the series resistances caused about 046 dB gain loss and the RC filter again an additional 067 dB If the amplifier had to be unconditionally stable (K>1) in the frequency range of 01 GHz to 80 GHz the increase of series resistances to 9Ω would cause an additional 040 dB gain loss and more attenuation to the drive signal The total decrease of gain due to stabilization would then be 153 dB from maximum gain of 1136–983 dB In the implemented form the maximum simulated gain is 1023 dB
34 Input signal timing in a physically large transistor
During simulations there was a noticeable phase shift between extreme fingers of the wide transistor consisting of12918 transistors with a width of 50lm each This phase shift caused partial overlap between output pulses and decreased the drain efficiency At that time the input network was made of a ladderlike structure shown as an example in Fig9(a) The distance of the line between FETA and FET B is close to 1 mm which as a pure line delay would result in about 20 ps of delay But the delay difference was more than 80 ps and also the pulse width of the input signal was larger than predicted Since the transistors do not switch simultaneously they start to
load each other and consume more power The reason for increased delay and widened pulse width is the signal dependent gate capacitance that causes considerable amount of second harmonic distortion in the unterminated ladderlike input network in Fig9(a) where the signal paths are almost equal in lengthThis improved the timing behaviour and the input waveform phasing in the simulations was nearly the same Only the pulse width was still somewhat large The equal input routing increased the drain efficiency of the amplifier from55 to 68 The effects of gate capacitance together with additional solutions to timing problems have been published in [10]
4 Final circuit
The amplifier die sized 196mm ×362 mm (W×L) was glued directly to a 6mmthick aluminium heat sink The goldplated printed circuit board (PCB) containing output matching network and some of the gate biasing network was mounted onto the heat sink Next the chip was wire bonded and SMA connectors were added to the circuit The final circuit schematic is shown in Fig10 where the dashed line is used to separate the on and offchip components Lower left side in the figure is an LCmatching network which is followed by an RCsink circuit The RCcircuit increases the stability of the amplifier by providing a wideband loading at higher frequencies In the gate bias circuit upwards from the matching circuit is the parallel RLCcircuit that is a high impedance at the operating frequency while the offchip parallel RCcircuit provides additional bias resistance in the low frequencies thus increasing the stability of the amplifier On the right side of the transistor the tuned output resonator together with the offchip matching circuit is shown Drain supply voltage is directed through a long transmission line that is a high impedance at the operation frequency
The parallel gate RC bias circuit and output matching circuit were implemented on the PCB which simplified the implemented chip shown in Fig 11 Upper left box (a) is the LC input matching lower left box (b) is the RLC bias network and on the right of the bias is the box (c)containing the RCsink circuit The equal length input lines are shown in the box (d) where the added series resistors(5Ωeach) show as wide sections in between the equal length lines The transistor set is shown in box (e) and it consists of 12 transistors each of which contain 18 fingers with a width of 50lm each The saturation current of the transistor is about 4 A On the right from the transistor set there is the output path together with the parallel resonator in the box (f) Bonding pads are below (Gate bias) on the left (RF in) and up (RF out and drain bias) Two or three bondwires are used to minimize series resistance and inductance and also to maximize current capability of the wires
41 The implemented amplifier
The implemented amplifier is shown in Fig12togetherwith a picture of the chip layout The resonator structure on the right side of the layout is clearly visible in the actual chip The PCB had to be drilled open and the aluminium base plate machined for levelling the chip along the PCB surface This way the bondwires are kept as short
as possible The PCB contains the impedance transforming network required by the output of the amplifier Further the supply is provided through long line that has relatively high impedance at the fundamental and has low resistance atDC A part of the gate biasing network is also located in the PCB The total size of the PCB is 171 mm×376 mm(Width9Length)
5 Measured performance
51 Measurement setups
A single tone measurement was used to measure the amplifier output power and efficiency An IFR 2025 signal generator and a buffer amplifier from MiniCircuits provided the drive signal level of 25 dBm The output was measured with a Rohde & Schwarz ZVA 8 vector spectrum analyser (VSA)
The load pull measurements were performed with Focus Microwaves MPT 1820 tuners that were applied both to the input and output of the amplifier As a source was Rohde &Schwarz SMU 200A with a buffer amplifier The input power levels were from 15 to 25 dBm The RF input and output powers were measured with Anritsu ML2438Apower meter with dual input The harmonic content of the spectrum and oscillation spikes were measured with Rohde& Schwarz FSQ 40 VSA
52 Tuning of the amplifier
In the first measurements the amplifier did not meet the simulated response Measurements gave only 096 W of output power at 1575 MHz when the simulated figures were 34 W of output power and drain efficiency of 70all at supply voltage of 55 V Our suspicion directed towards a scribe line that passed very close to the output resonator structure and possibly could couple the output to the input of the amplifier The scribe line was cut with an UVlaser but this had no effect to the frequency responseThe measured DC current of the amplifier was considerably higher than simulated suggesting that the load impedance of the switching stage was too low The impedance seen at the drain was increased by replacing a pair of 27 pF highQ ceramic capacitors (Amplifier A inTable1) in the external output matching network with one 29 pF capacitor (Amplifier B in Table1) This modification increased the output power to 2 W and the drain efficiency to 56 at the frequency of
1625 MHz The output power and efficiency in the frequency range of15–17 GHz is shown in Fig13 The output power is maintained within 053 dB in the desired frequency range(16265–16605 MHz) as shown in Fig 13 Within that same frequency band the drain efficiency stays above53 while the highest efficiency 56 is achieved at1626 MHz
By adjusting the supply voltage the efficiency of the amplifier can be increased even more which can be seen from Fig14 Drain efficiency increases steadily when supply is lowered At a supply voltage of 25 V and frequency of 1625 MHz the amplifier has a drain efficiency of 65 This implies that the amplifier can maintain an efficient operation also when used in an envelope elimination and restoration (EER) system The high peaks in at lowest supply voltages in Fig 14are caused by drive signal feedthrough that sums into the output signal
53 Load pull measurements
Measurements were performed with load pull system at16 GHz spot frequency to several modified amplifiers The differences between the amplifiers are shown in Table1In the next chapters we will mainly concentrate on amplifiers C and D for reasons that will be apparent later on Let us now discuss the amplifier C which is very similar to amplifier B measured earlier Tuners of the load pull system were connected to the outputs and inputs of the amplifier C The load tuning of fundamental second harmonic and third harmonic resulted in about 24 W of output power (338 dBm) while maintaining about 574 drainefficiency at this peak power spot
The fundamental load impedance in terms of power was at slightly higher impedance than the optimum drain efficiency point as shown in Fig15 where the 1 dB output power points (triangles) and5 unit efficiency points(circles) are shown The peak efficiency point in the figure is (a) (586) and peak power is (b) (339 dBm) The optimum efficiency area is rather large
Both of the load harmonics were even more relaxed and differences for example in output power had to be measured in tenths of decibels rather than in
decibels Furtherthe efficiency differences were measured in one or two percentage units instead of five to ten As an example the third harmonic optimum output points within 02 dB from maximum (triangles) and efficiency points within 2 units from maximum (circles) are shown in Fig 16 As it can beseen the third harmonic impedance is not as critical as the fundamental tone The optimum efficiency is marked with(a) and maximum output power is marked with (b) It should be noted that the adjustment of the third harmonic did not increase output power on the absolute scale nor the drain efficiency The peak output power value remained within 02 dB of the peak value of the fundamental load pull and the drain efficiency rose from 586 only to 598shown at the Smith chart point (a) in Fig16
The insensitivity of the amplifier to harmonic tuning is caused by the long drain bias line that is low impedance at the second harmonic and the low pass matching network at the output that attenuates the third harmonic
54 Source pull measurements
The source pull of the fundamental impedance did increase the output power and efficiency of amplifier C slightly The optimum drain efficiency (circles) and output power points(triangles) (a) and (b) respectively are shown Fig 17 The power points are within the limits of 02 dB and efficiency within a difference of 2 units The amplifier efficiency rose with the fundamental source tuning to 621 (point a)and the output to about 25 W (341 dBm point b) Harmonic source pull measurements showed that the harmonic impedances were not as critical as the fundamental This is due to the low pass input matching and the wideband RCsink circuit The RCsink circuit lowers the calculated magnitude of the impedance especially at high frequenciesas shown in Fig18(b) This has an effect to both second and third harmonic impedances The magnitude of the impedance without the RCsink is shown as a reference in Fig18(a) In both cases the input matching circuits were not included in the calculations
55 Stability of the amplifier
At first the amplifier A did show some unstable behaviour due to supply voltage modulation caused by insufficient bias decoupling at the drain The instability appeared at low input power levels as noise sidebands that lied on both sides of fundamental frequency When input power was lowered further on the amplifier did break into full scale oscillation As a cure the supply impedance was lowered by a large number of decoupling capacitors (4 ×470 pF)added to the drain In an EER application the supply modulator will provide low enough impedance at the drain
When the load pull was done to the amplifiers A C and D a spurious oscillation detection was applied at a level of50 dBc With this setup we were able to compare the sensitivity of different amplifiers to oscillations We found out that the RCsink circuit used in amplifiers A and C indeed improved stability especially in the low input power levels Data used for comparison was measured from amplifier D where the RCsink was cut using an ultraviolet laser The oscillation points of the fundamental impedance load pull with a low 15 dBm input power are shown in
Fig19
The oscillation sidebands detected are1701 and 1489 MHz If we compare this result to amplifier A the amount of found oscillation points is considerably smaller and the location of them is rather tightly spaced in the low impedance area as shown in Fig 20 The oscillation frequency in this case is 1568 MHz The amplifier A and amplifier
D had a different frequency for the modulating spurious components Without the damping circuit the modulating spurious was ca±100 MHz while with the damper the modulation appeared at about±30 MHz The probable reason for this lies in different drain bypassing as the amplifier D had less supply capacitance (4×470 pF less) The effect of this was studied by simulating from input to load transmission (S21) in the drain bias and matching network The circuit from amplifier D shows resonance at around 93 MHz as shown in Fig 21(a) while in the amplifier A the drain resonance is at 27 MHz frequency as shown in Fig21(b) As a reference a measured spectrum of amplifier A’s output is shown in Fig22 where the markers one and four are at±33
MHz distance from the fundamental frequency The input power in this case is15 dBm and fundamental load impedance is at one of the found oscillation impedances(Г0370Ø1653)The increase of chip decoupling capacitors (4×470 pF) in the case of amplifier A did lower the resonance from around100 MHz into 30 MHz region Inside the±30 MHz band there are also other oscillation tones which resemble a quasiperiodic solution and a chaos spectrum combinedExamples of quasiperiodic and chaos spectrums are shown for example in [11] An interesting point of the resonance seen was that the large electrolytic capacitors applied to the bias supply did not attenuate the about 30 MHz resonancedue to its high inductance
56 Additional findings
Switching amplifiers are dependent on sufficient amount of gate drive and
variations in the drive signal affect quickly the performance of the amplifier In our case small variations in transistor pinchoff voltage resulted in 2–3 dB differences in gain between the amplifiers when bias voltage was kept constant Such clear differences could beseen in vector network analyser measurements with a 0 dBm input drive More constant results could be derived by adjusting the small drain bias currents to equal when no drive signal was applied Now the measurements of gain were matched within 08 dB
6 Summary
A tuned RF power amplifier has been designed for operation in a frequency band of 16–17 GHz The amplifier was designed empirically to have nonoverlapping drain voltage and current pulses and the required resonant circuit was implemented onchip A new position of the DCblocking capacitor genereted a resonator trap that stabilizes the amplifier below the desired band and a gate RCsink circuit was used to stabilize the amplifier at higher frequencies Further equal length input lines were implemented to equalize the timing of gate signals
The stability of the amplifier was evaluated through simulations of large signal Sparameters and stability circles Additional resistances together with an RCsink circuit had to be applied to keep the stable output SWR range at more than 2261 The amplifier was implemented onto a GaAs substrate with depletion mode high electron mobility transistors (FETs) The implemented amplifier delivers 2 W of output power while maintaining 56 drain efficiency The frequency response is within 053 dB at a frequency band of 16265–16605 MHz while the drain efficiency stays above 53 in this desired band
The amplifier was also measured with a load pull system at a spot frequency of 16 GHz With the help of tuners the amplifier achieved about 25 W of output power and 62efficiency Load pull also revealed the amplifier’s sensitivity to oscillations at small drive levels It was found out that the output matching network has a lowfrequency resonance that might contribute to the unstable behaviourThe implemented gate sink was verified to stabilize the circuit
It might be a beneficial idea to design an input LCtrap circuit tuned to the second harmonic since there is second harmonic content at the input which widens the input waveform in the time domain creating problems in terms of efficiency and power Further increasing the third harmonic content could make the input waveform more squarelike which is a desired feature in switching amplifiers
Acknowledgements： This work has been supported by The Academy of Finland Infotech Oulu Graduate School TriQuint Semiconductor Inc Nokia Foundation Tauno Tonning FoundationUlla Tuominen Foundation and The foundation of Riitta and Jorma J Takanen My special thanks to the personnel of the Department of Electronics and Telecommunications in the Norwegian University of Science and Technology (NTNU) and to the personnel of the Micro and Nanotechnology Centre in the University of Oulu
References
1 Cripps S C (2006)RF power amplifiers for wireless communications (2 edn) 685 Canton Street Norwood MA 02062Artech House Inc
2 Raab F (1977) Idealized operation of the class e tuned power amplifierCircuits and Systems IEEE Transactions on 24(12)725–735
3 Sokal N O & Sokal A D (1975) Class e–a new class of high efficiency tuned singleended switching power amplifiersIEEE Journal of SolidState Circuits 10(3) 168–176
4 Mury T & Fusco V (2005) Serieslparalleltuned classepower amplifier analysis InProc European microwave conference(Vol 1 p 4) doi101109EUMC20051608890
5 Tayrani R (2007) A spectrally pure 50 w high pae (6–12 ghz)gan monolithic class e power amplifier for advanced tr modulesIn Proc IEEE radio frequency integrated circuits (RFIC) symposium(pp 581–584) doi101109RFIC2007380951
6 Hietakangas S Rautio T & Rahkonen T (2006) 1 ghz class erf power amplifier for a polar transmitter In Proc 24th norchipconference(pp 5–9) doi101109NORCHP2006329232
7 Hietakangas S Rautio T & Rahkonen T (2008) One ghz class e rf power amplifier for a polar transmitterAnalog Integrated Circuits and Signal Processing An International Journal54(2) 85–94 doi101007s104700079109x
8 Triquint Semiconductor Inc (2007)TQPED 05 um ED pHEMT foundry service (22 edn) httpwwwtriquintcomprodservfoundrydocsTQPEDv2_2pdf
9 Kazimierczuk M & Tabisz W (1989) Class ce highefficiency tuned power amplifier Circuits and Systems IEEE Transactions on 36(3) 421–428 doi1011093117589
10 Hietakangas S Typpo J & Rahkonen T (2008) Effects of input routing in switched rf amplifiers In Proc workshop on integrated nonlinear microwave and millimetrewave circuits INMMIC 2008(pp 35–38) doi101109INMMIC20084745708
11 Suarez A Jeon S & Rutledge D (2006) Stability analysis andstabilization of power amplifiers IEEE Microwave Magazine7(5) 51–65 doi101109MWM2006247915
Simo Hietakangaswas born in Alaha¨rma ¨ Finland in 1980 He received the MSc degree in Electrical Engineering from the University of Oulu Oulu Finland in 2005 and is currently working toward the PhDdegree at the University of Oulu His technical interests lie in the field of analysis and modeling of switching RF power amplifiers
Jukka Typpo¨was born in OuluFinland in 1963 He received his MSc degree in University of Oulu in 1992 and his PhDdegree in Norwegian University of Science and Technology in2003 Currently he works as a research fellow at Norwegian University of Science and Technology Department of Electronics and Telecommunications His current research topic is integrated RF power amplifiers
Timo Rahkonenwas born inJyva ¨skyla ¨ Finland in 1962 He received the Diploma EngineerLicentiate and Doctor of Technology degrees from the University of Oulu Oulu Finlandin 1986 1991 and 1994respectively He is currently a Professor of circuit theory and circuit design with the University of Oulu where he conducts research on linearization and errorcorrection techniques for RF power amplifiers and
AD and DA converters
16GHZ2W集成式调谐射频式接收功率放器设计
摘：篇文种指定运行行频率1626516605MHZ范围国际海事卫星集成调谐功率放器描述放器基拓扑结构行优化逆E类放器修改类放器通新位置安装直流隔离电容通调整电容尺寸提高低预期波段频率稳定性外新安放位置减少排水负载损失电路中高电流宽电感宽度芯片谐振器高Q值手指电容必该放器实现砷化镓（GaAs）集成电路（IC）交付2 W输出功率漏极效率约 56％测量包括信号源负载达进步改善该放器性输入驱动电进行时调查稳定性
关键词：逆E级功率放器激振荡偏置网络
1介绍
天高功率通信系统传统线性放器性低效率限制事实推动更高效放器研究兴趣E级[13]逆E级[4]外较高输出功率需求意味着更高峰值电流电压漏极集电极电路创建求高晶体两击穿值单片微波集成电路（MMIC）源电路限导电性限电容应付热效果通仔细设计MMIC达化外晶体新兴技术似承受更电流密度峰值电压[5]设计高功率器件时技术选择变越越重
文目显示开关高功率射频（RF）功率放器（PA）具集成输出脉整形设计验第二章中介绍E级逆E级操作重新审视两种拓扑结构间差异第三章介绍输入输出电路稳定电路设计提供提示关指晶体输入端减少时差方式第四章出终原理实现芯片片第五章中实测性通两基单音测量设备现代化负载拉移系统采功调谐器（MPT）进行报告部分提供关稳定电路问题文章讨摘
2E级反E级放器
E级逆E级视开关放器理想情况两者晶体驱动开关闭该开关动作产生系列电压电流脉输出脉相移会彼重叠理想非重叠导致晶体具100％漏极效率操作典E类漏极波形化电源电流电压DC值展示图1实线化漏极电流波形虚线化漏极电压E类佳操作求零电压开关（ZVS）中漏极电压衍生物变零晶体导通前进行逆E类波形已交换位置便图1中实线波形漏极电压虚线漏电流佳操作改变零电流开关（ZCS）中电流衍生物利变零晶体进入非导通阶段前逆E级相典实现优点漏极峰值电压传统E级较低输出电路中电感值较MMIC芯片实现节省面积通常更电器串联电阻（ESR）[4]外接收串联电感作振电路部分性寄生电抗引起阻尼振排出波形[67]优势选择逆E类拓扑结构作研究出发点原然调谐执行传统逆E级然类似脉操作
3调谐功率放器设计
31砷化镓IC工艺
IC工艺TriQuint半导体公司伪形态高电子迁移率晶体(pHEMT) 命名TQPED工艺该工艺采增强型耗型场效应两晶体（FET）具05lm长光学光刻门例子中耗型晶体耗型晶体具27千兆赫渡频率（f t）漏极 栅极击穿电压1605 V08V晶体模型中标称夹断点TOM3 FET模型工业中特点：镍铬合金（镍铬）电阻精度宗高值电阻高价值金属 绝缘体 金属（MIM）电容12层厚度全球金属层[8]
32振器设计
图2中原始逆E级设计中调谐拓扑结构存差图3示阻断电容器Cs位置
图2示原始安装提供隔直流分两方：输出（负载） 更重会阻止直接通电感Lp直流电流路径情况中阻塞电容器谐振电路方图3示中铯妨碍直流电流流电感Lp输出（负载）直接方法基电流流输出会传递阻塞隔电容器直流阻塞电容器现做更情况中100 pF减少低50 pF意味着芯片面积节省作辅助效果够调整稳定陷阱需频率（第三章32）时保持良放器性直流阻隔设计现稍微容易峰值电流流入阻断分支较外漏极负载间ESR更Cs元器件中基波电流振幅分
122 A图3中出联谐振器结构总峰值电流
传统逆E类标注[ 4 ] 数16 GHz功率输出 3 W导致较芯片面积较高Q 10总电容较（ 635 PF） 高峰值电流（约6 A ）电感变巨获合理芯片元件值设计逐渐[4]中设计程转较低负载电阻Q值增加振频率结束提供整齐重叠标注电流电压脉合理尺寸源器件终更接C级E基负荷原逆E类模拟终元件值[ 9 ]分立元件模型片外低通阻抗匹配网络50Ω导致尺寸：阻性负载4Ω CTOT 30 pF电感 LP 022 NHL终设计忽略铯降低50 pF影响整体性调整稳定低载波陷波面图 8 示带开关晶体（具18×50μm05μm手指电容12联晶体）估计56 W输出功率72％漏极效率总仿真结果现面挑战现维护良输出功率效率时取代（PDK）制程设计套件（PDK）组件代理想电路元件时增加稳定电路拓扑结构设计问题电感物理设计降低Q值电流幅度然高（42 A峰值）感应器概需200lm宽金属线保持34弯度电感器中心开理04 nH总电容Q值进步减少点减少电阻损耗总电容分成12联高Q电容器谐振器结构绘制布局导入25D场模拟S参数进行模拟离散模拟原型进行较S参数模拟较阻抗数卸载相位幅度显示图45分布式谐振器相位幅值数两数字标记虚线谐振器相位幅度遵循相曲线完整放器进行模拟漏极效率约70％输出功率概34 W输出功率减少解释寄生电阻稳定电路导致漏极效率出意料降低Q验输出电路设计方式仿真实现分布式谐振器图6示
33 稳定化放器
该放器显示种信号S参数（LSSP）模拟时稳定倾终稳定必须通LSSP基础稳定电路里进行评估条件稳定（K>1）没重损失实现稳定电路画整055 GHz频率范围次仿真种稳定电路必须补偿振铃性首先分立电容器Cs调谐50 pF直生成输出谐振器陷约12千兆赫频率助面通罗莱特K系数图7示频率茅屋频率达稳定 50 pF值选定输出功率较损失良稳定性电容器Cs调谐影响示图8中电容器调谐30〜70 pF范围
进步说5Ω串联电阻添加图9（b）示3栅极线保持放器稳定范围461输出驻波（SWR）外宽频带RC宿电路包括放器输入端减少较高频率增益稳定输出SWR范围增益增加RC滤波器2261根模拟串联电阻引起约046 dB增益损耗RC滤波器额外067分贝果放器必须条件稳定（K>1）01千兆赫80千兆赫频率范围串联电阻增加9Ω导致该驱动信号额外040分贝增益损失更衰减1136983分贝增益然增益稳定总跌幅降153分贝执行仿真程中模拟增益1023分贝
34体积较晶体输入时钟信号
仿真期间广泛晶体组成12918晶体50lm宽度极端手指间明显相移种相移引起部分重叠输出脉间降低漏极效率时输入网络作出示图9（a）例子阶梯状结构 FETA场效应B间线距离接1毫米作纯粹线延迟导致约20 ps延迟延迟差超80 ps样输入信号脉宽度预测晶体时切换开始加载方消耗较电究原增加延迟展宽脉宽度信号赖栅极电容导致图9（a）未结束阶梯状输入网络相数量二次谐波失真中信号路径相等长度改进时序行输入波形相位模拟相脉宽度点相等输入路增加放器55漏极效率68％栅极电容附加解决方案时序
问题影响已发表[10]
4终电路
该放器模具尺寸196毫米× 362毫米（宽×长）直接粘6mm厚铝制散热片含输出匹配网络栅极偏置网络镀金印刷电路板（PCB）安装散热器未芯片键合线SMA连接器添加电路中终电路示意图示图10 中虚线分隔芯片外组件左侧图中RC宿电路LC匹配网络该RC电路提供宽带装载较高频率增加放器稳定性栅极偏置电路述匹配电路联RLC电路工作频率高阻抗片联RC电路提供额外偏置电阻低频率增加稳定性放器右侧晶体该调谐输出谐振器芯片外匹配电路起示出漏极供电电压通长传输线操作频率高阻抗定
行栅极RC偏置电路输出匹配电路中电路板简化实施芯片实现图 11示左框（a）LC输入匹配左框（b）RLC偏置网络偏置右侧包含RC宿电路方块（c）示长度相等输入线显示框中（d）中中添加串联电阻（5Ωeach）显示宽部分中相等长度行间晶体集显示话框（E）12晶体
包含18手指50lm宽度晶体饱电流约4 A晶体集合右边输出路径连框中（f）该联谐振器焊盘低（门偏置）左侧（RF中）高达（RF输出漏极偏置）两三接合线量减少串联电阻电感时限度提高导线输送电流力
41 实现放器放器
实现放器图12示芯片布局图起实际芯片右侧布置谐振器结构清晰见PCB必须钻开铝基板加工PCB表面整芯片样接合线保持短印刷电路板包含放器输出需阻抗变换网络外电源具相高阻抗基波具低电阻ATDC长线路提供门偏置网络部分位PCB PCB总171㎜×376毫米
5测试性
51测试计划
单音测量测量放器输出功率效率IFR2025信号发生器微型电路缓放器提供25 dBm驱动信号电输出罗德施瓦茨ZVA8矢量频谱分析仪（VSA）测量
负载牵引测量进行该均施加放器输入输出聚焦微波MPT1820调谐器作源罗德施瓦茨公司SMU200A带缓放器输入功
率水分15〜25 dBm RF输入输出功率测量安立ML2438A功率测定仪双输入频谱振荡尖峰谐波含量测定Rohde＆Schwarz公司FSQ40 VSA
52调谐放器
述第测量放器符合仿真响应测量096 W输出功率1575 MHz时仿真数字分34 W输出功率漏极效率70％电压源55 V怀疑电源电压指该传递非常接输出划线谐振器结构耦合输出放器输入端划线切割紫外线激光必须测量放器直流电流频率相应没结果模拟高表明开关级负载阻抗太低漏阻抗增加更换27 pF高Q值陶瓷电容（放器A表1）外部输出网络29 pF电容匹配（放器B表1）该变形增输出功率2瓦漏极效率56％625兆赫频率输出功率频率范围1517 GHz效率示图13输出功率保持053分贝需频率范围（1626516605兆赫）图13示保持相频带漏极效率保持53％高效率56％达1626兆赫
通调节供电电压放器效率进步增加图14中出供电电压降低漏极效率稳步升25 V1625 MHz频率电源电压时放器具65％漏极效率意味着该放器保持高效操作包络消恢复（EER）系统中时峰值电压低电源电压图 14根输出信号驱动信号馈通
53负载迁移测试
测量负载拉移系统16GHz频率点进行修改放器放器间差异显示表接章节中集中放器CD原显易见现讨放器C非常相似放器B早期测量负载拉移系统调谐器连接放器C输出输入基波二次谐波三次谐波负载调谐导致约24W输出功率（338dBm）时保持约574％效率峰值功率点
电力方面基负载阻抗佳漏极效率点稍高阻抗图15示中1分贝输出功率点（三角形）5％单元效率点（圆圈）示出图中峰值效率点（a）（586％）峰值功率（B）（339 dBm）佳效率区域相
两负载谐波甚更放松输出功率实施例区测定分贝十分分贝外效率差异测定两百分单位代五十作例子第三谐波佳输出02分贝2％单位（圆圈）（三角形）效率分点显示图16见三次谐波阻抗关重基音佳效率标（a）输出功率标（b）示应指出三次谐波调整没增加绝尺度漏极效率输出功率峰值输出功率值保持基负载牵引漏极效率峰值
02dB仅仅升586％598％图16史密斯圆图（a）点示
放器谐波调谐敏感性长漏极偏置线第二谐波低阻抗低通匹配网络该衰减三次谐波输出引起
54 元迁移测量
根阻抗源拉提高输出功率放器Ç稍微效率佳漏极效率（圆圈）输出功率点（三角形） （ a）（ b）中分示出图 17 电源点范围2 ％单位差02分贝效率限制该放器效率提高根源泉调整621 ％ （点）输出约25瓦（ 341 dBm时 b点） 谐波源拉测量结果表明谐波阻抗样重基础低通输入匹配宽带RC宿电路RC 宿电路降低阻抗尤高频率计算幅度图18（ b）示具效果二次三次谐波阻抗未RC漏极阻抗图18中（ a）示两种情况输入匹配电路包括计算中
55放器稳定性
起初放器A确实显示稳定行引起足耦偏置漏极电压调制稳定出现低输入功率水噪声边带骗基频两侧输入功率进步调时放器入全面振荡作治疗电源阻抗量耦电容（4×470 PF）降低加漏效应中电源调制器提供足够低阻抗漏级
负载拉做放器ACD中寄生振荡检测50 dBc水施加采种设置够放器灵敏度进行较振荡发现RC宿电路放器AC确实改善稳定性尤低输入功率水较数放器D中RC漏极紫外线激光切割测定低15 dBm输入功率基阻抗负载牵引振荡点示图19
振荡边带检测are17011489兆赫果较该结果放器A发现振荡点数量相位置相紧密间隔低阻抗区域中图示 20种情况振荡频率1568兆赫放器A放器D调制虚拟原件：阻尼电路虚拟调制频率约±100兆赫然存阻尼时调制出现约±30兆赫现象原漏级旁路放器D较少供应电容（4×470 pF更少）通输入加载传输（S21）中漏极偏压匹配网络研究现象影响放器D中电路显示出谐振约93兆赫时反应图21（a）放器A漏极振27 MHz频率图21（b）示示作参考放器A输出测定光谱示图22中标记物1四正处基频±33兆赫距离该图中种情况输入功率15 dBm基负载阻抗发现振荡阻抗（Г0370O 1653）芯片耦电容（4×470 pF）放器A情况增加降低约100兆赫30兆赫区域做振时反应±30 MHz频段类似准周期解决方案准周期混沌光谱组合例准周期混沌光谱[11]显示振趣问题高电感系数施加偏置供应型电解电容器没减弱约30 MHz振
56额外发现
开关放器赖栅极驱动器足够数量种样驱动信号快速影响放器性例子中晶体夹断电压微变化导致23分贝时增益差放器间时电压保持恒定种明显差异发现矢量网络分析仪测量0 dBm输入驱动时更加恒定结果推断通调节微漏极偏置电流相等时没驱动信号施加现增益测量结果08分贝匹配
6总结
调谐射频（RF）功率放器已设计1617 GHz范围频带操作放器根验设计具非重叠漏极电压电流脉求谐振电路已芯片应阻隔直流电容器新位置会产生谐振陷阱谐振陷阱放器稳定低需频带范围栅极
RC宿电路稳定放器工作较高频率外长度相等输入线实施时钟门信号
放器稳定性通信号S参数稳定圆模拟评价附加电阻RC宿电路起施加保持输出SWR超2261稳定放器应GaAs衬底具耗型高电子迁移率晶体（FET已应放器提供输出功率2瓦时保持56％漏极效率频率响应053分贝频带1626516605兆赫范围漏极效率保持高53％期频带
16 GHz频率放器测量负载牵引系统调谐器放器帮助实现输出功率约25 W62％效率负载牵拉驱动电时放器灵敏度振荡程度关发现输出匹配网络具导致稳定表现低频振实行门沉验证稳定电路
益想法设计调谐第二谐波输入LC陷波电路中存该加宽输入波形时域效率功率方面产生问题输入第二谐波时进步增加第三谐波含量输入波形变更加趋方形开关放器希特征
感谢：篇文 The Academy of Finland Infotech Oulu Graduate School TriQuint Semiconductor Inc Nokia Foundation Tauno Tonning FoundationUlla Tuominen Foundation and The foundation of Riitta and Jorma J Takanen支持 the Department of Electronics and Telecommunications in the Norwegian University of Science and Technology (NTNU) and to the personnel of the Micro and Nanotechnology Centre in the University of Oulu表示衷感谢
参考文献
Cripps S C (2006)RF power amplifiers for wireless communications (2 edn) 685 Canton Street Norwood MA 02062Artech House Inc
2 Raab F (1977) Idealized operation of the class e tuned power amplifierCircuits and Systems IEEE Transactions on 24(12)725–735
3 Sokal N O & Sokal A D (1975) Class e–a new class of high efficiency tuned singleended switching power amplifiersIEEE Journal of SolidState Circuits 10(3) 168–176
4 Mury T & Fusco V (2005) Serieslparalleltuned classepower amplifier analysis InProc European microwave conference(Vol 1 p 4) doi101109EUMC20051608890
5 Tayrani R (2007) A spectrally pure 50 w high pae (6–12 ghz)gan monolithic class e power amplifier for advanced tr modulesIn Proc IEEE radio frequency integrated circuits (RFIC) symposium(pp 581–584) doi101109RFIC2007380951
6 Hietakangas S Rautio T & Rahkonen T (2006) 1 ghz class erf power amplifier for a polar transmitter In Proc 24th norchipconference(pp 5–9) doi101109NORCHP2006329232
7 Hietakangas S Rautio T & Rahkonen T (2008) One ghz class e rf power amplifier for a polar transmitterAnalog Integrated Circuits and Signal Processing An International Journal54(2) 85–94 doi101007s104700079109x
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Simo Hietakangaswas born in Alaha¨rma ¨ Finland in 1980 He received the MSc degree in Electrical Engineering from the University of Oulu Oulu Finland in 2005 and is currently working toward the PhDdegree at the University of Oulu His technical interests lie in the field of analysis and modeling of switching RF power amplifiers
Jukka Typpo¨was born in OuluFinland in 1963 He received his MSc degree in University of Oulu in 1992 and his PhDdegree in Norwegian University of Science and Technology in2003 Currently he works as a research fellow at Norwegian University of Science and Technology Department of Electronics and Telecommunications His current research topic is integrated RF power amplifiers
Timo Rahkonenwas born inJyva ¨skyla ¨ Finland in 1962 He received the Diploma EngineerLicentiate and Doctor of Technology degrees from the University of Oulu Oulu Finlandin 1986 1991 and 1994respectively He is currently a Professor of circuit theory and circuit design with the University of Oulu where he conducts research on linearization and errorcorrection techniques for RF power amplifiers and AD and DA converters
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