51单片机英文资料


    September 1993
    Order Number 270251004
    MCSÉ 51 Family of
    Microcontrollers
    Architectural OverviewInformation in this document is provided in connection with Intel products Intel assumes no liability whatsoev
    er including infringement of any patent or copyright for sale and use of Intel products except as provided in
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    COPYRIGHT © INTEL CORPORATION 1996MCSÉ51 Family of Microcontrollers
    Architectural Overview
    CONTENTS PAGE
    INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1
    CHMOS Devices ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2
    MEMORY ORGANIZATION IN MCSÉ51
    DEVICES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2
    Logical Separation of Program and Data
    Memory ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2
    Program Memory ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
    Data Memory ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
    THE MCSÉ51 INSTRUCTION SET ÀÀÀÀÀÀÀÀ 5
    Program Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
    Addressing Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
    CONTENTS PAGE
    Arithmetic Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
    Logical Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
    Data Transfers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
    Boolean Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
    Jump Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
    CPU TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
    Machine Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
    Interrupt Structure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
    ADDITIONAL REFERENCES ÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
    3MCSÉ51 ARCHITECTURAL OVERVIEW
    INTRODUCTION
    The 8051 is the original member of the MCSÉ51 family and is the core for all MCS51 devices The features of the
    8051 core are
    # 8bit CPU optimized for control applications
    # Extensive Boolean processing (singlebit logic) capabilities
    # 64K Program Memory address space
    # 64K Data Memory address space
    # Onchip Program Memory
    # 128 bytes of onchip Data RAM
    # 32 bidirectional and individually addressable IO lines
    # Two 16bit timercounters
    # Full duplex UART
    # 6source5vector interrupt structure with two priority levels
    # Onchip clock oscillator
    The basic architectural structure of this 8051 core is shown in Figure 1
    270251–1
    Figure 1 Block Diagram of the 8051 Core
    1MCSÉ51 ARCHITECTURAL OVERVIEW
    270251–2
    Figure 2 MCSÉ51 Memory Structure
    CHMOS Devices
    Functionally the CHMOS devices (designated with
    C’’ in the middle of the device name) are all fully
    compatible with the 8051 but being CMOS draw less
    current than an HMOS counterpart To further exploit
    the power savings available in CMOS circuitry two re
    duced power modes are added
    # Softwareinvoked Idle Mode during which the CPU
    is turned off while the RAM and other onchip
    peripherals continue operating In this mode cur
    rent draw is reduced to about 15 of the current
    drawn when the device is fully active
    # Softwareinvoked Power Down Mode during which
    all onchip activities are suspended The onchip
    RAM continues to hold its data In this mode the
    device typically draws less than 10 mA
    Although the 80C51BH is functionally compatible with
    its HMOS counterpart specific differences between the
    two types of devices must be considered in the design of
    an application circuit if one wishes to ensure complete
    interchangeability between the HMOS and CHMOS
    devices These considerations are discussed in the Ap
    plication Note AP252 Designing with the
    80C51BH’’
    For more information on the individual devices and
    features refer to the Hardware Descriptions and Data
    Sheets of the specific device
    MEMORY ORGANIZATION IN
    MCSÉ51 DEVICES
    Logical Separation of Program and
    Data Memory
    All MCS51 devices have separate address spaces for
    Program and Data Memory as shown in Figure 2 The
    logical separation of Program and Data Memory allows
    the Data Memory to be accessed by 8bit addresses
    which can be more quickly stored and manipulated by
    an 8bit CPU Nevertheless 16bit Data Memory ad
    dresses can also be generated through the DPTR regis
    ter
    Program Memory can only be read not written to
    There can be up to 64K bytes of Program Memory In
    the ROM and EPROM versions of these devices the
    lowest 4K 8K or 16K bytes of Program Memory are
    provided onchip Refer to Table 1 for the amount of
    onchip ROM (or EPROM) on each device In the
    ROMless versions all Program Memory is external
    The read strobe for external Program Memory is the
    signal PSEN (Program Store Enable)
    2MCSÉ51 ARCHITECTURAL OVERVIEW
    Data Memory occupies a separate address space from
    Program Memory Up to 64K bytes of external RAM
    can be addressed in the external Data Memory space
    The CPU generates read and write signals RD and
    WR as needed during external Data Memory accesses
    External Program Memory and external Data Memory
    may be combined if desired by applying the RD and
    PSEN signals to the inputs of an AND gate and using
    the output of the gate as the read strobe to the external
    ProgramData memory
    Program Memory
    Figure 3 shows a map of the lower part of the Program
    Memory After reset the CPU begins execution from
    location 0000H
    As shown in Figure 3 each interrupt is assigned a fixed
    location in Program Memory The interrupt causes the
    CPU to jump to that location where it commences exe
    cution of the service routine External Interrupt 0 for
    example is assigned to location 0003H If External In
    terrupt 0 is going to be used its service routine must
    begin at location 0003H If the interrupt is not going to
    be used its service location is available as general pur
    pose Program Memory
    270251–3
    Figure 3 MCSÉ51 Program Memory
    The interrupt service locations are spaced at 8byte in
    tervals 0003H for External Interrupt 0 000BH for
    Timer 0 0013H for External Interrupt 1 001BH for
    Timer 1 etc If an interrupt service routine is short
    enough (as is often the case in control applications) it
    can reside entirely within that 8byte interval Longer
    service routines can use a jump instruction to skip over
    subsequent interrupt locations if other interrupts are in
    use
    The lowest 4K (or 8K or 16K or 32K) bytes of Pro
    gram Memory can be either in the onchip ROM or in
    an external ROM This selection is made by strapping
    the EA (External Access) pin to either VCC or VSS
    In the 4K byte ROM devices if the EA pin is strapped
    to VCC then program fetches to addresses 0000H
    through 0FFFH are directed to the internal ROM Pro
    gram fetches to addresses 1000H through FFFFH are
    directed to external ROM
    In the 8K byte ROM devices EA e VCC selects ad
    dresses 0000H through 1FFFH to be internal and ad
    dresses 2000H through FFFFH to be external
    In the 16K byte ROM devices EA e VCC selects ad
    dresses 0000H through 3FFFH to be internal and ad
    dresses 4000H through FFFFH to be external
    If the EA pin is strapped to VSS then all program
    fetches are directed to external ROM The ROMless
    parts must have this pin externally strapped to VSS to
    enable them to execute properly
    The read strobe to external ROM PSEN is used for all
    external program fetches PSEN is not activated for in
    ternal program fetches
    270251–4
    Figure 4 Executing from External
    Program Memory
    The hardware configuration for external program exe
    cution is shown in Figure 4 Note that 16 IO lines
    (Ports 0 and 2) are dedicated to bus functions during
    external Program Memory fetches Port 0 (P0 in Figure
    4) serves as a multiplexed addressdata bus It emits
    the low byte of the Program Counter (PCL) as an ad
    dress and then goes into a float state awaiting the arriv
    al of the code byte from the Program Memory During
    the time that the low byte of the Program Counter is
    valid on P0 the signal ALE (Address Latch Enable)
    clocks this byte into an address latch Meanwhile Port
    2 (P2 in Figure 4) emits the high byte of the Program
    Counter (PCH) Then PSEN strobes the EPROM and
    the code byte is read into the microcontroller
    3MCSÉ51 ARCHITECTURAL OVERVIEW
    Program Memory addresses are always 16 bits wide
    even though the actual amount of Program Memory
    used may be less than 64K bytes External program
    execution sacrifices two of the 8bit ports P0 and P2 to
    the function of addressing the Program Memory
    Data Memory
    The right half of Figure 2 shows the internal and exter
    nal Data Memory spaces available to the MCS51 user
    Figure 5 shows a hardware configuration for accessing
    up to 2K bytes of external RAM The CPU in this case
    is executing from internal ROM Port 0 serves as a
    multiplexed addressdata bus to the RAM and 3 lines
    of Port 2 are being used to page the RAM The CPU
    generates RD and WR signals as needed during exter
    nal RAM accesses
    270251–5
    Figure 5 Accessing External Data Memory
    If the Program Memory is Internal the Other
    Bits of P2 are Available as IO
    There can be up to 64K bytes of external Data Memo
    ry External Data Memory addresses can be either 1 or
    2 bytes wide Onebyte addresses are often used in con
    junction with one or more other IO lines to page the
    RAM as shown in Figure 5 Twobyte addresses can
    also be used in which case the high address byte is
    emitted at Port 2
    270251–6
    Figure 6 Internal Data Memory
    Internal Data Memory is mapped in Figure 6 The
    memory space is shown divided into three blocks
    which are generally referred to as the Lower 128 the
    Upper 128 and SFR space
    Internal Data Memory addresses are always one byte
    wide which implies an address space of only 256 bytes
    However the addressing modes for internal RAM can
    in fact accommodate 384 bytes using a simple trick
    Direct addresses higher than 7FH access one memory
    space and indirect addresses higher than 7FH access a
    different memory space Thus Figure 6 shows the Up
    per 128 and SFR space occupying the same block of
    addresses 80H through FFH although they are physi
    cally separate entities
    270251–7
    Figure 7 The Lower 128 Bytes of Internal RAM
    The Lower 128 bytes of RAM are present in all
    MCS51 devices as mapped in Figure 7 The lowest 32
    bytes are grouped into 4 banks of 8 registers Program
    instructions call out these registers as R0 through R7
    Two bits in the Program Status Word (PSW) select
    which register bank is in use This allows more efficient
    use of code space since register instructions are shorter
    than instructions that use direct addressing
    270251–8
    Figure 8 The Upper 128 Bytes of Internal RAM
    4MCSÉ51 ARCHITECTURAL OVERVIEW
    270251–10
    Figure 10 PSW (Program Status Word) Register in MCSÉ51 Devices
    The next 16 bytes above the register banks form a block
    of bitaddressable memory space The MCS51 instruc
    tion set includes a wide selection of singlebit instruc
    tions and the 128 bits in this area can be directly ad
    dressed by these instructions The bit addresses in this
    area are 00H through 7FH
    All of the bytes in the Lower 128 can be accessed by
    either direct or indirect addressing The Upper 128
    (Figure 8) can only be accessed by indirect addressing
    The Upper 128 bytes of RAM are not implemented in
    the 8051 but are in the devices with 256 bytes of RAM
    (See Table 1)
    Figure 9 gives a brief look at the Special Function Reg
    ister (SFR) space SFRs include the Port latches tim
    ers peripheral controls etc These registers can only be
    accessed by direct addressing In general all MCS51
    microcontrollers have the same SFRs as the 8051 and
    at the same addresses in SFR space However enhance
    ments to the 8051 have additional SFRs that are not
    present in the 8051 nor perhaps in other proliferations
    of the family
    270251–9
    Figure 9 SFR Space
    Sixteen addresses in SFR space are both byte and bit
    addressable The bitaddressable SFRs are those whose
    address ends in 000B The bit addresses in this area are
    80H through FFH
    THE MCSÉ51 INSTRUCTION SET
    All members of the MCS51 family execute the same
    instruction set The MCS51 instruction set is opti
    mized for 8bit control applications It provides a vari
    ety of fast addressing modes for accessing the internal
    RAM to facilitate byte operations on small data struc
    tures The instruction set provides extensive support for
    onebit variables as a separate data type allowing direct
    bit manipulation in control and logic systems that re
    quire Boolean processing
    An overview of the MCS51 instruction set is presented
    below with a brief description of how certain instruc
    tions might be used References to the assembler’’ in
    this discussion are to Intel’s MCS51 Macro Assembler
    ASM51 More detailed information on the instruction
    set can be found in the MCS51 Macro Assembler Us
    er’s Guide (Order No 9800937 for ISIS Systems Order
    No 122752 for DOS Systems)
    Program Status Word
    The Program Status Word (PSW) contains several
    status bits that reflect the current state of the CPU The
    PSW shown in Figure 10 resides in SFR space It con
    tains the Carry bit the Auxiliary Carry (for BCD oper
    ations) the two register bank select bits the Overflow
    flag a Parity bit and two userdefinable status flags
    The Carry bit other than serving the functions of a
    Carry bit in arithmetic operations also serves as the
    Accumulator’’ for a number of Boolean operations
    5MCSÉ51 ARCHITECTURAL OVERVIEW
    The bits RS0 and RS1 are used to select one of the four
    register banks shown in Figure 7 A number of instruc
    tions refer to these RAM locations as R0 through R7
    The selection of which of the four banks is being re
    ferred to is made on the basis of the bits RS0 and RS1
    at execution time
    The Parity bit reflects the number of 1s in the Accumu
    lator P e 1 if the Accumulator contains an odd num
    ber of 1s and P e 0 if the Accumulator contains an
    even number of 1s Thus the number of 1s in the Accu
    mulator plus P is always even
    Two bits in the PSW are uncommitted and may be used
    as general purpose status flags
    Addressing Modes
    The addressing modes in the MCS51 instruction set
    are as follows
    DIRECT ADDRESSING
    In direct addressing the operand is specified by an 8bit
    address field in the instruction Only internal Data
    RAM and SFRs can be directly addressed
    INDIRECT ADDRESSING
    In indirect addressing the instruction specifies a register
    which contains the address of the operand Both inter
    nal and external RAM can be indirectly addressed
    The address register for 8bit addresses can be R0 or
    R1 of the selected register bank or the Stack Pointer
    The address register for 16bit addresses can only be the
    16bit data pointer’’ register DPTR
    REGISTER INSTRUCTIONS
    The register banks containing registers R0 through R7
    can be accessed by certain instructions which carry a
    3bit register specification within the opcode of the in
    struction Instructions that access the registers this way
    are code efficient since this mode eliminates an address
    byte When the instruction is executed one of the eight
    registers in the selected bank is accessed One of four
    banks is selected at execution time by the two bank
    select bits in the PSW
    REGISTERSPECIFIC INSTRUCTIONS
    Some instructions are specific to a certain register For
    example some instructions always operate on the Ac
    cumulator or Data Pointer etc so no address byte is
    needed to point to it The opcode itself does that In
    structions that refer to the Accumlator as A assemble
    as accumulatorspecific opcodes
    IMMEDIATE CONSTANTS
    The value of a constant can follow the opcode in Pro
    gram Memory For example
    MOV A Ý100
    loads the Accumulator with the decimal number 100
    The same number could be specified in hex digits as
    64H
    INDEXED ADDRESSING
    Only Program Memory can be accessed with indexed
    addressing and it can only be read This addressing
    mode is intended for reading lookup tables in Program
    Memory A 16bit base register (either DPTR or the
    Program Counter) points to the base of the table and
    the Accumulator is set up with the table entry number
    The address of the table entry in Program Memory is
    formed by adding the Accumulator data to the base
    pointer
    Another type of indexed addressing is used in the case
    jump’’ instruction In this case the destination address
    of a jump instruction is computed as the sum of the
    base pointer and the Accumulator data
    Arithmetic Instructions
    The menu of arithmetic instructions is listed in Table 2
    The table indicates the addressing modes that can be
    used with each instruction to access the kbytel oper
    and For example the ADD Akbytel instruction can
    be written as
    ADD A7FH (direct addressing)
    ADD A@R0 (indirect addressing)
    ADD AR7 (register addressing)
    ADD AÝ127 (immediate constant)
    The execution times listed in Table 2 assume a 12 MHz
    clock frequency All of the arithmetic instructions exe
    cute in 1 ms except the INC DPTR instruction which
    takes 2 ms and the Multiply and Divide instructions
    which take 4 ms
    Note that any byte in the internal Data Memory space
    can be incremented or decremented without going
    through the Accumulator
    One of the INC instructions operates on the 16bit
    Data Pointer The Data Pointer is used to generate
    16bit addresses for external memory so being able to
    increment it in one 16bit operation is a useful feature
    The MUL AB instruction multiplies the Accumulator
    by the data in the B register and puts the 16bit product
    into the concatenated B and Accumulator registers
    6MCSÉ51 ARCHITECTURAL OVERVIEW
    Table 2 A List of the MCSÉ51 Arithmetic Instructions
    Mnemonic Operation Addressing Modes Execution
    Dir Ind Reg Imm Time (ms)
    ADD Akbytel A e A a kbytel XX X X 1
    ADDC Akbytel A e A a kbytel a CXXX X 1
    SUBB Akbytel A e A b kbytel b CXXXX 1
    INC A A e A a 1 Accumulator only 1
    INC kbytelkbytel e kbytel a 1X X X 1
    INC DPTR DPTR e DPTR a 1 Data Pointer only 2
    DEC A A e A b 1 Accumulator only 1
    DEC kbytelkbytel e kbytel b 1X X X 1
    MUL AB BA e B x A ACC and B only 4
    DIV AB A e Int [AB] ACC and B only 4
    B e Mod [AB]
    DA A Decimal Adjust Accumulator only 1
    The DIV AB instruction divides the Accumulator by
    the data in the B register and leaves the 8bit quotient
    in the Accumulator and the 8bit remainder in the B
    register
    Oddly enough DIV AB finds less use in arithmetic
    divide’’ routines than in radix conversions and pro
    grammable shift operations An example of the use of
    DIV AB in a radix conversion will be given later In
    shift operations dividing a number by 2n shifts its n
    bits to the right Using DIV AB to perform the division
    completes the shift in 4 ms and leaves the B register
    holding the bits that were shifted out
    The DA A instruction is for BCD arithmetic opera
    tions In BCD arithmetic ADD and ADDC instruc
    tions should always be followed by a DA A operation
    to ensure that the result is also in BCD Note that DA
    A will not convert a binary number to BCD The DA
    A operation produces a meaningful result only as the
    second step in the addition of two BCD bytes
    Table 3 A List of the MCSÉ51 Logical Instructions
    Mnemonic Operation Addressing Modes Execution
    Dir Ind Reg Imm Time (ms)
    ANL Akbytel A e A AND kbytel XX X X 1
    ANL kbytelA kbytel e kbytel AND A X 1
    ANL kbytelÝdata kbytel e kbytel AND Ýdata X 2
    ORL Akbytel A e A OR kbytel XX X X 1
    ORL kbytelA kbytel e kbytel OR A X 1
    ORL kbytelÝdata kbytel e kbytel OR Ýdata X 2
    XRL Akbytel A e A XOR kbytel XX X X 1
    XRL kbytelA kbytel e kbytel XOR A X 1
    XRL kbytelÝdata kbytel e kbytel XOR Ýdata X 2
    CRL A A e 00H Accumulator only 1
    CPL A A e NOT A Accumulator only 1
    RL A Rotate ACC Left 1 bit Accumulator only 1
    RLC A Rotate Left through Carry Accumulator only 1
    RR A Rotate ACC Right 1 bit Accumulator only 1
    RRC A Rotate Right through Carry Accumulator only 1
    SWAP A Swap Nibbles in A Accumulator only 1
    7MCSÉ51 ARCHITECTURAL OVERVIEW
    Logical Instructions
    Table 3 shows the list of MCS51 logical instructions
    The instructions that perform Boolean operations
    (AND OR Exclusive OR NOT) on bytes perform the
    operation on a bitbybit basis That is if the Accumu
    lator contains 00110101B and kbytel contains
    01010011B then
    ANL Akbytel
    will leave the Accumulator holding 00010001B
    The addressing modes that can be used to access the
    kbytel operand are listed in Table 3 Thus the ANL
    Akbytel instruction may take any of the forms
    ANL A7FH (direct addressing)
    ANL A@R1 (indirect addressing)
    ANL AR6 (register addressing)
    ANL AÝ53H (immediate constant)
    All of the logical instructions that are Accumulator
    specific execute in 1ms (using a 12 MHz clock) The
    others take 2 ms
    Note that Boolean operations can be performed on any
    byte in the lower 128 internal Data Memory space or
    the SFR space using direct addressing without having
    to use the Accumulator The XRL kbytel Ýdata in
    struction for example offers a quick and easy way to
    invert port bits as in
    XRL P1Ý0FFH
    If the operation is in response to an interrupt not using
    the Accumulator saves the time and effort to stack it in
    the service routine
    The Rotate instructions (RL A RLC A etc) shift the
    Accumulator 1 bit to the left or right For a left rota
    tion the MSB rolls into the LSB position For a right
    rotation the LSB rolls into the MSB position
    The SWAP A instruction interchanges the high and
    low nibbles within the Accumulator This is a useful
    operation in BCD manipulations For example if the
    Accumulator contains a binary number which is known
    to be less than 100 it can be quickly converted to BCD
    by the following code
    MOV BÝ10
    DIV AB
    SWAP A
    ADD AB
    Dividing the number by 10 leaves the tens digit in the
    low nibble of the Accumulator and the ones digit in the
    B register The SWAP and ADD instructions move the
    tens digit to the high nibble of the Accumulator and
    the ones digit to the low nibble
    Data Transfers
    INTERNAL RAM
    Table 4 shows the menu of instructions that are avail
    able for moving data around within the internal memo
    ry spaces and the addressing modes that can be used
    with each one With a 12 MHz clock all of these in
    structions execute in either 1 or 2 ms
    The MOV kdestl ksrcl instruction allows data to
    be transferred between any two internal RAM or SFR
    locations without going through the Accumulator Re
    member the Upper 128 byes of data RAM can be ac
    cessed only by indirect addressing and SFR space only
    by direct addressing
    Note that in all MCS51 devices the stack resides in
    onchip RAM and grows upwards The PUSH instruc
    tion first increments the Stack Pointer (SP) then copies
    the byte into the stack PUSH and POP use only direct
    addressing to identify the byte being saved or restored
    Table 4 A List of the MCSÉ51 Data Transfer Instructions that Access Internal Data Memory Space
    Mnemonic Operation Addressing Modes Execution
    Dir Ind Reg Imm Time (ms)
    MOV Aksrcl A e ksrcl XX X X 1
    MOV kdestlA kdestl e AXXX1
    MOV kdestl ksrclkdestl e ksrcl XX X X 2
    MOV DPTRÝdata16 DPTR e 16bit immediate constant X 2
    PUSH ksrcl INC SP MOV @SP’’ksrcl X2
    POP kdestl MOV kdestl@SP’’ DEC SP X 2
    XCH Akbytel ACC and kbytel exchange data X X X 1
    XCHD A@Ri ACC and @Ri exchange low nibbles X 1
    8MCSÉ51 ARCHITECTURAL OVERVIEW
    but the stack itself is accessed by indirect addressing
    using the SP register This means the stack can go into
    the Upper 128 if they are implemented but not into
    SFR space
    In devices that do not implement the Upper 128 if the
    SP points to the Upper 128 PUSHed bytes are lost and
    POPped bytes are indeterminate
    The Data Transfer instructions include a 16bit MOV
    that can be used to initialize the Data Pointer (DPTR)
    for lookup tables in Program Memory or for 16bit
    external Data Memory accesses
    The XCH A kbytel instruction causes the Accumu
    lator and addressed byte to exchange data The XCHD
    A@Ri instruction is similar but only the low nibbles
    are involved in the exchange
    To see how XCH and XCHD can be used to facilitate
    data manipulations consider first the problem of shift
    ing an 8digit BCD number two digits to the right Fig
    ure 11 shows how this can be done using direct MOVs
    and for comparison how it can be done using XCH
    instructions To aid in understanding how the code
    works the contents of the registers that are holding the
    BCD number and the content of the Accumulator are
    shown alongside each instruction to indicate their
    status after the instruction has been executed
    2A 2B 2C 2D 2E ACC
    MOV A2EH 00 12 34 56 78 78
    MOV 2EH2DH 00 12 34 56 56 78
    MOV 2DH2CH 00 12 34 34 56 78
    MOV 2CH2BH 00 12 12 34 56 78
    MOV 2BHÝ0 000012345678
    (a) Using direct MOVs 14 bytes 9 ms
    2A 2B 2C 2D 2E ACC
    CLRA 001234567800
    XCH A2BH 00 00 34 56 78 12
    XCH A2CH 00 00 12 56 78 34
    XCH A2DH 00 00 12 34 78 56
    XCH A2EH 00 00 12 34 56 78
    (b) Using XCHs 9 bytes 5 ms
    Figure 11 Shifting a BCD Number
    Two Digits to the Right
    After the routine has been executed the Accumulator
    contains the two digits that were shifted out on the
    right Doing the routine with direct MOVs uses 14 code
    bytes and 9 ms of execution time (assuming a 12 MHz
    clock) The same operation with XCHs uses less code
    and executes almost twice as fast
    To rightshift by an odd number of digits a onedigit
    shift must be executed Figure 12 shows a sample of
    code that will rightshift a BCD number one digit us
    ing the XCHD instruction Again the contents of the
    registers holding the number and of the Accumulator
    are shown alongside each instruction
    2A 2B 2C 2D 2E ACC
    MOV R1Ý2EH 00 12 34 56 78 XX
    MOV R0Ý2DH 00 12 34 56 78 XX
    loop for R1 e 2EH
    LOOP MOV A@R1 00 12 34 56 78 78
    XCHD A@R0 00 12 34 58 78 76
    SWAP A 00 12 34 58 78 67
    MOV @R1A 00 12 34 58 67 67
    DEC R1 00 12 34 58 67 67
    DEC R0 00 12 34 58 67 67
    CJNE R1Ý2AHLOOP
    loop for R1 e 2DH 00 12 38 45 67 45
    loop for R1 e 2CH 00 18 23 45 67 23
    loop for R1 e 2BH 08 01 23 45 67 01
    CLR A 080123456700
    XCH A2AH 00 01 23 45 67 08
    Figure 12 Shifting a BCD Number
    One Digit to the Right
    First pointers R1 and R0 are set up to point to the two
    bytes containing the last four BCD digits Then a loop
    is executed which leaves the last byte location 2EH
    holding the last two digits of the shifted number The
    pointers are decremented and the loop is repeated for
    location 2DH The CJNE instruction (Compare and
    Jump if Not Equal) is a loop control that will be de
    scribed later
    The loop is executed from LOOP to CJNE for R1 e
    2EH 2DH 2CH and 2BH At that point the digit that
    was originally shifted out on the right has propagated
    to location 2AH Since that location should be left with
    0s the lost digit is moved to the Accumulator
    9MCSÉ51 ARCHITECTURAL OVERVIEW
    EXTERNAL RAM
    Table 5 shows a list of the Data Transfer instructions
    that access external Data Memory Only indirect ad
    dressing can be used The choice is whether to use a
    onebyte address @Ri where Ri can be either R0 or
    R1 of the selected register bank or a twobyte address
    @DPTR The disadvantage to using 16bit addresses if
    only a few K bytes of external RAM are involved is
    that 16bit addresses use all 8 bits of Port 2 as address
    bus On the other hand 8bit addresses allow one to
    address a few K bytes of RAM as shown in Figure 5
    without having to sacrifice all of Port 2
    All of these instructions execute in 2 ms with a
    12 MHz clock
    Table 5 A List of the MCSÉ51 Data
    Transfer Instructions that Access
    External Data Memory Space
    Address Mnemonic Operation Execution
    Width Time (ms)
    8 bits MOVX A@Ri Read external 2RAM @Ri
    8 bits MOVX @RiA Write external 2RAM @Ri
    16 bits MOVX A@DPTR Read external 2RAM @DPTR
    16 bits MOVX @DPTRA Write external 2RAM @DPTR
    Note that in all external Data RAM accesses the Ac
    cumulator is always either the destination or source of
    the data
    The read and write strobes to external RAM are acti
    vated only during the execution of a MOVX instruc
    tion Normally these signals are inactive and in fact if
    they’re not going to be used at all their pins are avail
    able as extra IO lines More about that later
    LOOKUP TABLES
    Table 6 shows the two instructions that are available
    for reading lookup tables in Program Memory Since
    these instructions access only Program Memory the
    lookup tables can only be read not updated The mne
    monic is MOVC for move constant’’
    If the table access is to external Program Memory then
    the read strobe is PSEN
    Table 6 The MCSÉ51 Lookup
    Table Read Instructions
    Mnemonic Operation Execution
    Time (ms)
    MOVC A@AaDPTR Read Pgm Memory 2
    at (AaDPTR)
    MOVC A@AaPC Read Pgm Memory 2
    at (AaPC)
    The first MOVC instruction in Table 6 can accommo
    date a table of up to 256 entries numbered 0 through
    255 The number of the desired entry is loaded into the
    Accumulator and the Data Pointer is set up to point to
    beginning of the table Then
    MOVC A@AaDPTR
    copies the desired table entry into the Accumulator
    The other MOVC instruction works the same way ex
    cept the Program Counter (PC) is used as the table
    base and the table is accessed through a subroutine
    First the number of the desired entry is loaded into the
    Accumulator and the subroutine is called
    MOV AENTRYÐNUMBER
    CALL TABLE
    The subroutine TABLE’’ would look like this
    TABLE MOVC A@AaPC
    RET
    The table itself immediately follows the RET (return)
    instruction in Program Memory This type of table can
    have up to 255 entries numbered 1 through 255 Num
    ber 0 can not be used because at the time the MOVC
    instruction is executed the PC contains the address of
    the RET instruction An entry numbered 0 would be
    the RET opcode itself
    Boolean Instructions
    MCS51 devices contain a complete Boolean (singlebit)
    processor The internal RAM contains 128 addressable
    bits and the SFR space can support up to 128 other
    addressable bits All of the port lines are bitaddress
    able and each one can be treated as a separate single
    bit port The instructions that access these bits are not
    just conditional branches but a complete menu of
    move set clear complement OR and AND instruc
    tions These kinds of bit operations are not easily ob
    tained in other architectures with any amount of byte
    oriented software
    10MCSÉ51 ARCHITECTURAL OVERVIEW
    Table 7 A List of the MCSÉ51
    Boolean Instructions
    Mnemonic Operation Execution
    Time (ms)
    ANL Cbit C e C AND bit 2
    ANL Cbit C e C AND NOT bit 2
    ORL Cbit C e C OR bit 2
    ORL Cbit C e C OR NOT bit 2
    MOV Cbit C e bit 1
    MOV bitC bit e C2
    CLR C C e 01
    CLR bit bit e 01
    SETB C C e 11
    SETB bit bit e 11
    CPL C C e NOT C 1
    CPL bit bit e NOT bit 1
    JC rel Jump if C e 12
    JNC rel Jump if C e 02
    JB bitrel Jump if bit e 12
    JNB bitrel Jump if bit e 02
    JBC bitrel Jump if bit e 1 CLR bit 2
    The instruction set for the Boolean processor is shown
    in Table 7 All bit accesses are by direct addressing Bit
    addresses 00H through 7FH are in the Lower 128 and
    bit addresses 80H through FFH are in SFR space
    Note how easily an internal flag can be moved to a port
    pin
    MOV CFLAG
    MOV P10C
    In this example FLAG is the name of any addressable
    bit in the Lower 128 or SFR space An IO line (the
    LSB of Port 1 in this case) is set or cleared depending
    on whether the flag bit is 1 or 0
    The Carry bit in the PSW is used as the singlebit Accu
    mulator of the Boolean processor Bit instructions that
    refer to the Carry bit as C assemble as Carryspecific
    instructions (CLR C etc) The Carry bit also has a
    direct address since it resides in the PSW register
    which is bitaddressable
    Note that the Boolean instruction set includes ANL
    and ORL operations but not the XRL (Exclusive OR)
    operation An XRL operation is simple to implement in
    software Suppose for example it is required to form
    the Exclusive OR of two bits
    C e bit1 XRL bit2
    The software to do that could be as follows
    MOV Cbit1
    JNB bit2OVER
    CPL C
    OVER (continue)
    First bit1 is moved to the Carry If bit2 e 0 then C
    now contains the correct result That is bit1 XRL bit2
    e bit1 if bit2 e 0 On the other hand if bit2 e 1C
    now contains the complement of the correct result It
    need only be inverted (CPL C) to complete the opera
    tion
    This code uses the JNB instruction one of a series of
    bittest instructions which execute a jump if the ad
    dressed bit is set (JC JB JBC) or if the addressed bit is
    not set (JNC JNB) In the above case bit2 is being
    tested and if bit2 e 0 the CPL C instruction is jumped
    over
    JBC executes the jump if the addressed bit is set and
    also clears the bit Thus a flag can be tested and cleared
    in one operation
    All the PSW bits are directly addressable so the Parity
    bit or the general purpose flags for example are also
    available to the bittest instructions
    RELATIVE OFFSET
    The destination address for these jumps is specified to
    the assembler by a label or by an actual address in
    Program Memory However the destination address
    assembles to a relative offset byte This is a signed
    (two’s complement) offset byte which is added to the
    PC in two’s complement arithmetic if the jump is exe
    cuted
    The range of the jump is therefore b128 to a127 Pro
    gram Memory bytes relative to the first byte following
    the instruction
    11MCSÉ51 ARCHITECTURAL OVERVIEW
    Jump Instructions
    Table 8 shows the list of unconditional jumps
    Table 8 Unconditional Jumps
    in MCSÉ51 Devices
    Mnemonic Operation Execution
    Time (ms)
    JMP addr Jump to addr 2
    JMP @AaDPTR Jump to AaDPTR 2
    CALL addr Call subroutine at addr 2
    RET Return from subroutine 2
    RETI Return from interrupt 2
    NOP No operation 1
    The Table lists a single JMP addr’’ instruction but in
    fact there are threeÐSJMP LJMP and AJMPÐwhich
    differ in the format of the destination address JMP is a
    generic mnemonic which can be used if the program
    mer does not care which way the jump is encoded
    The SJMP instruction encodes the destination address
    as a relative offset as described above The instruction
    is 2 bytes long consisting of the opcode and the relative
    offset byte The jump distance is limited to a range of
    b128 to a127 bytes relative to the instruction follow
    ing the SJMP
    The LJMP instruction encodes the destination address
    as a 16bit constant The instruction is 3 bytes long
    consisting of the opcode and two address bytes The
    destination address can be anywhere in the 64K Pro
    gram Memory space
    The AJMP instruction encodes the destination address
    as an 11bit constant The instruction is 2 bytes long
    consisting of the opcode which itself contains 3 of the
    11 address bits followed by another byte containing the
    low 8 bits of the destination address When the instruc
    tion is executed these 11 bits are simply substituted for
    the low 11 bits in the PC The high 5 bits stay the same
    Hence the destination has to be within the same 2K
    block as the instruction following the AJMP
    In all cases the programmer specifies the destination
    address to the assembler in the same way as a label or
    as a 16bit constant The assembler will put the destina
    tion address into the correct format for the given in
    struction If the format required by the instruction will
    not support the distance to the specified destination ad
    dress a Destination out of range’’ message is written
    into the List file
    The JMP @AaDPTR instruction supports case
    jumps The destination address is computed at execu
    tion time as the sum of the 16bit DPTR register and
    the Accumulator Typically DPTR is set up with the
    address of a jump table and the Accumulator is given
    an index to the table In a 5way branch for example
    an integer 0 through 4 is loaded into the Accumulator
    The code to be executed might be as follows
    MOV DPTRÝJUMPÐTABLE
    MOV AINDEXÐNUMBER
    RL A
    JMP @AaDPTR
    The RL A instruction converts the index number (0
    through 4) to an even number on the range 0 through 8
    because each entry in the jump table is 2 bytes long
    JUMPÐTABLE
    AJMP CASEÐ0
    AJMP CASEÐ1
    AJMP CASEÐ2
    AJMP CASEÐ3
    AJMP CASEÐ4
    Table 8 shows a single CALL addr’’ instruction but
    there are two of themÐLCALL and ACALLÐwhich
    differ in the format in which the subroutine address is
    given to the CPU CALL is a generic mnemonic which
    can be used if the programmer does not care which way
    the address is encoded
    The LCALL instruction uses the 16bit address format
    and the subroutine can be anywhere in the 64K Pro
    gram Memory space The ACALL instruction uses the
    11bit format and the subroutine must be in the same
    2K block as the instruction following the ACALL
    In any case the programmer specifies the subroutine
    address to the assembler in the same way as a label or
    as a 16bit constant The assembler will put the address
    into the correct format for the given instructions
    Subroutines should end with a RET instruction which
    returns execution to the instruction following the
    CALL
    RETI is used to return from an interrupt service rou
    tine The only difference between RET and RETI is
    that RETI tells the interrupt control system that the
    interrupt in progress is done If there is no interrupt in
    progress at the time RETI is executed then the RETI
    is functionally identical to RET
    Table 9 shows the list of conditional jumps available to
    the MCS51 user All of these jumps specify the desti
    nation address by the relative offset method and so are
    limited to a jump distance of b128 to a127 bytes from
    the instruction following the conditional jump instruc
    tion Important to note however the user specifies to
    the assembler the actual destination address the same
    way as the other jumps as a label or a 16bit constant
    12MCSÉ51 ARCHITECTURAL OVERVIEW
    Table 9 Conditional Jumps in MCSÉ51 Devices
    Mnemonic Operation Addressing Modes Execution
    Dir Ind Reg Imm Time (ms)
    JZ rel Jump if A e 0 Accumulator only 2
    JNZ rel Jump if A i 0 Accumulator only 2
    DJNZ kbytelrel Decrement and jump if not zero X X 2
    CJNE Akbytelrel Jump if A i kbytel XX2
    CJNE kbytelÝdatarel Jump if kbytel i Ýdata X X 2
    There is no Zero bit in the PSW The JZ and JNZ
    instructions test the Accumulator data for that condi
    tion
    The DJNZ instruction (Decrement and Jump if Not
    Zero) is for loop control To execute a loop N times
    load a counter byte with N and terminate the loop with
    a DJNZ to the beginning of the loop as shown below
    for N e 10
    MOV COUNTERÝ10
    LOOP (begin loop)
    *
    *
    *
    (end loop)
    DJNZ COUNTERLOOP
    (continue)
    The CJNE instruction (Compare and Jump if Not
    Equal) can also be used for loop control as in Figure 12
    Two bytes are specified in the operand field of the in
    struction The jump is executed only if the two bytes
    are not equal In the example of Figure 12 the two
    bytes were the data in R1 and the constant 2AH The
    initial data in R1 was 2EH Every time the loop was
    executed R1 was decremented and the looping was to
    continue until the R1 data reached 2AH
    Another application of this instruction is in greater
    than less than’’ comparisons The two bytes in the op
    erand field are taken as unsigned integers If the first is
    less than the second then the Carry bit is set (1) If the
    first is greater than or equal to the second then the
    Carry bit is cleared
    CPU TIMING
    All MCS51 microcontrollers have an onchip oscillator
    which can be used if desired as the clock source for the
    CPU To use the onchip oscillator connect a crystal or
    ceramic resonator between the XTAL1 and XTAL2
    pins of the microcontroller and capacitors to ground as
    shown in Figure 13
    270251–11
    Figure 13 Using the OnChip Oscillator
    270251–12
    A HMOS or CHMOS
    270251–13
    B HMOS Only
    270251–14
    C CHMOS Only
    Figure 14 Using an External Clock
    13MCSÉ51 ARCHITECTURAL OVERVIEW
    Examples of how to drive the clock with an external
    oscillator are shown in Figure 14 Note that in the
    HMOS devices (8051 etc) the signal at the XTAL2 pin
    actually drives the internal clock generator In the
    CHMOS devices (80C51BH etc) the signal at the
    XTAL1 pin drives the internal clock generator If only
    one pin is going to be driven with the external oscillator
    signal make sure it is the right pin
    The internal clock generator defines the sequence of
    states that make up the MCS51 machine cycle
    Machine Cycles
    A machine cycle consists of a sequence of 6 states
    numbered S1 through S6 Each state time lasts for two
    oscillator periods Thus a machine cycle takes 12 oscil
    lator periods or 1 ms if the oscillator frequency is
    12 MHz
    Each state is divided into a Phase 1 half and a Phase 2
    half Figure 15 shows the fetchexecute sequences in
    270251–15
    Figure 15 State Sequences in MCSÉ51 Devices
    14MCSÉ51 ARCHITECTURAL OVERVIEW
    states and phases for various kinds of instructions Nor
    mally two program fetches are generated during each
    machine cycle even if the instruction being executed
    doesn’t require it If the instruction being executed
    doesn’t need more code bytes the CPU simply ignores
    the extra fetch and the Program Counter is not incre
    mented
    Execution of a onecycle instruction (Figure 15A and
    B) begins during State 1 of the machine cycle when the
    opcode is latched into the Instruction Register A sec
    ond fetch occurs during S4 of the same machine cycle
    Execution is complete at the end of State 6 of this ma
    chine cycle
    The MOVX instructions take two machine cycles to
    execute No program fetch is generated during the sec
    ond cycle of a MOVX instruction This is the only time
    program fetches are skipped The fetchexecute se
    quence for MOVX instructions is shown in Figure
    15(D)
    The fetchexecute sequences are the same whether the
    Program Memory is internal or external to the chip
    Execution times do not depend on whether the Pro
    gram Memory is internal or external
    Figure 16 shows the signals and timing involved in pro
    gram fetches when the Program Memory is external If
    Program Memory is external then the Program Memo
    ry read strobe PSEN is normally activated twice per
    machine cycle as shown in Figure 16(A)
    If an access to external Data Memory occurs as shown
    in Figure 16(B) two PSENs are skipped because the
    address and data bus are being used for the Data Mem
    ory access
    Note that a Data Memory bus cycle takes twice as
    much time as a Program Memory bus cycle Figure 16
    shows the relative timing of the addresses being emitted
    at Ports 0 and 2 and of ALE and PSEN ALE is used
    to latch the low address byte from P0 into the address
    latch
    270251–16
    Figure 16 Bus Cycles in MCSÉ51 Devices Executing from External Program Memory
    15MCSÉ51 ARCHITECTURAL OVERVIEW
    When the CPU is executing from internal Program
    Memory PSEN is not activated and program address
    es are not emitted However ALE continues to be acti
    vated twice per machine cycle and so is available as a
    clock output signal Note however that one ALE is
    skipped during the execution of the MOVX instruction
    Interrupt Structure
    The 8051 core provides 5 interrupt sources 2 external
    interrupts 2 timer interrupts and the serial port inter
    rupt What follows is an overview of the interrupt
    structure for the 8051 Other MCS51 devices have ad
    ditional interrupt sources and vectors as shown in Ta
    ble 1 Refer to the appropriate chapters on other devic
    es for further information on their interrupts
    INTERRUPT ENABLES
    Each of the interrupt sources can be individually en
    abled or disabled by setting or clearing a bit in the SFR
    (MSB) (LSB)
    EAÐÐESET1EX1ET0EX0
    Enable bit e 1 enables the interrupt
    Enable bit e 0 disables it
    Symbol Position Function
    EA IE7 disables all interrupts If EA e 0 no
    interrupt will be acknowledged If EA
    e 1 each interrupt source is
    individually enabled or disabled by
    setting or clearing its enable bit
    Ð IE6 reserved*
    Ð IE5 reserved*
    ES IE4 Serial Port Interrupt enable bit
    ET1 IE3 Timer 1 Overflow Interrupt enable bit
    EX1 IE2 External Interrupt 1 enable bit
    ET0 IE1 Timer 0 Overflow Interrupt enable bit
    EX0 IE0 External Interrupt 0 enable bit
    *These reserved bits are used in other MCS51 devices
    Figure 17 IE (Interrupt Enable)
    Register in the 8051
    named IE (Interrupt Enable) This register also con
    tains a global disable bit which can be cleared to dis
    able all interrupts at once Figure 17 shows the IE reg
    ister for the 8051
    INTERRUPT PRIORITIES
    Each interrupt source can also be individually pro
    grammed to one of two priority levels by setting or
    clearing a bit in the SFR named IP (Interrupt Priority)
    Figure 18 shows the IP register in the 8051
    A lowpriority interrrupt can be interrupted by a high
    priority interrupt but not by another lowpriority inter
    rupt A highpriority interrupt can’t be interrupted by
    any other interrupt source
    If two interrupt requests of different priority levels are
    received simultaneously the request of higher priority
    level is serviced If interrupt requests of the same priori
    ty level are received simultaneously an internal polling
    sequence determines which request is serviced Thus
    within each priority level there is a second priority
    structure determined by the polling sequence
    Figure 19 shows for the 8051 how the IE and IP regis
    ters and the polling sequence work to determine which
    if any interrupt will be serviced
    (MSB) (LSB)
    ÐÐÐPSPT1PX1PT0PX0
    Priority bit e 1 assigns high priority
    Priority bit e 0 assigns low priority
    Symbol Position Function
    Ð IP7 reserved*
    Ð IP6 reserved*
    Ð IP5 reserved*
    PS IP4 Serial Port interrupt priority bit
    PT1 IP3 Timer 1 interrupt priority bit
    PX1 IP2 External Interrupt 1 priority bit
    PT0 IP1 Timer 0 interrupt priority bit
    PX0 IP0 External Interrupt 0 priority bit
    *These reserved bits are used in other MCS51 devices
    Figure 18 IP (Interrupt Priority)
    Register in the 8051
    16MCSÉ51 ARCHITECTURAL OVERVIEW
    270251–17
    Figure 19 8051 Interrupt Control System
    In operation all the interrupt flags are latched into the
    interrupt control system during State 5 of every ma
    chine cycle The samples are polled during the follow
    ing machine cycle If the flag for an enabled interrupt is
    found to be set (1) the interrupt system generates an
    LCALL to the appropriate location in Program Memo
    ry unless some other condition blocks the interrupt
    Several conditions can block an interrupt among them
    that an interrupt of equal or higher priority level is
    already in progress
    The hardwaregenerated LCALL causes the contents of
    the Program Counter to be pushed onto the stack and
    reloads the PC with the beginning address of the service
    routine As previously noted (Figure 3) the service rou
    tine for each interrupt begins at a fixed location
    Only the Program Counter is automatically pushed
    onto the stack not the PSW or any other register Hav
    ing only the PC be automatically saved allows the pro
    grammer to decide how much time to spend saving
    which other registers This enhances the interrupt re
    sponse time albeit at the expense of increasing the pro
    grammer’s burden of responsibility As a result many
    interrupt functions that are typical in control applica
    tionsÐtoggling a port pin for example or reloading a
    timer or unloading a serial bufferÐcan often be com
    pleted in less time than it takes other architectures to
    commence them
    SIMULATING A THIRD PRIORITY LEVEL IN
    SOFTWARE
    Some applications require more than the two priority
    levels that are provided by onchip hardware in
    MCS51 devices In these cases relatively simple soft
    ware can be written to produce the same effect as a
    third priority level
    First interrupts that are to have higher priority than 1
    are assigned to priority 1 in the IP (Interrupt Priority)
    register The service routines for priority 1 interrupts
    that are supposed to be interruptible by priority 2’’
    interrupts are written to include the following code
    PUSH IE
    MOV IEÝMASK
    CALL LABEL
    *******
    (execute service routine)
    *******
    POP IE
    RET
    LABEL RETI
    17MCSÉ51 ARCHITECTURAL OVERVIEW
    As soon as any priority 1 interrupt is acknowledged
    the IE (Interrupt Enable) register is redefined so as to
    disable all but priority 2’’ interrupts Then a CALL to
    LABEL executes the RETI instruction which clears
    the priority 1 interruptinprogress flipflop At this
    point any priority 1 interrupt that is enabled can be
    serviced but only priority 2’’ interrupts are enabled
    POPping IE restores the original enable byte Then a
    normal RET (rather than another RETI) is used to
    terminate the service routine The additional software
    adds 10 ms (at 12 MHz) to priority 1 interrupts
    ADDITIONAL REFERENCES
    The following application notes are found in the Em
    bedded Control Applications handbook (Order Num
    ber 270648)
    1 AP69 An Introduction to the Intel MCSÉ51 Sin
    gleChip Microcomputer Family’’
    2 AP70 Using the Intel MCSÉ51 Boolean Process
    ing Capabilities’’
    18

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