AL422 Data Sheets
(Revision V11)
AL422

AL422B January 23 2001 2
Amendments (Since April 2 1999)

051399 DCAC characteristics (including current consumption) updated
070299 Pinout diagram (50) and DC external load (74) modified
080399 Description about TST pin added in sections 60 & 81
090299 832 rewritten
102699 Capacitance provided in the AC characteristics section
121599 Remove TST pin restriction
011801 1 Revised section 832 Read Enable during Reset Cycles to 832 The Proper
Manipulation of FIFO Access
2 Add section 833 Single Field Write with Multiple Read Operation
3 Add section 834 One Field Delay Line (The Old Data Read)



AL422

AL422B January 23 2001 3
AL422 3MBits FIFO Field Memory


Contents
10 Description ________________________________________________________________ 4
20 Features___________________________________________________________________ 4
30 Applications________________________________________________________________ 4
40 Ordering Information________________________________________________________ 4
50 Pinout Diagram ____________________________________________________________ 5
60 Pin Description _____________________________________________________________ 5
70 Electrical Characteristics _____________________________________________________ 6
71 Absolute Maximum Ratings ________________________________________________________ 6
72 Recommended Operating Conditions ________________________________________________ 6
73 DC Characteristics _______________________________________________________________ 6
74 AC Characteristics _______________________________________________________________ 7
75 Timing Diagrams_________________________________________________________________ 9
80 Functional Description______________________________________________________ 13
81 Memory Operation ______________________________________________________________ 14
82 5V and 33V applications _________________________________________________________ 15
83 Application Notes _______________________________________________________________ 16
831 Irregular ReadWrite _________________________________________________________________ 16
832 The Proper Manipulation of FIFO Access _________________________________________________ 17
833 Single Field Write with Multiple Read Operation___________________________________________ 17
834 One Field Delay Line (The Old Data Read) _______________________________________________ 17
90 Mechanical Drawing _______________________________________________________ 19
AL422

AL422B January 23 2001 4

10 Description

The AL422 consists of 3Mbits of DRAM and is configured as 393216 words x 8 bit FIFO (first in
first out) The interface is very userfriendly since all complicated DRAM operations are already
managed by the internal DRAM controller

Current sources of similar memory (field memory) in the market provide limited memory size which
is only enough for holding one TV field but not enough to hold a whole PC video frame which
normally contains 640x480 or 720x480 bytes The AverLogic AL422 provides 50 more memory
to support high resolution for digital PC graphics or video applications The 50 increase in speed
also expands the range of applications

20 Features

· 384K (393216) x 8 bits FIFO organization
· Support VGA CCIR NTSC PAL and
HDTV resolutions
· Independent readwrite operations (different
IO data rates acceptable)
· High speed asynchronous serial access
· Readwrite cycle time 20ns
· Access time 15ns
· Output enable control (data skipping)
· Self refresh
· 5V or 33V power supply
· Standard 28pin SOP package
30 Applications

· Multimedia systems
· Video capture systems
· Video editing systems
· Scan rate converters
· TV’s picture in picture feature
· Time base correction (TBC)
· Frame synchronizer
· Digital video camera
· Buffer for communications systems






40 Ordering Information

Part number Package Power Supply Status
AL422B 28pin plastic SOP +5+33 volt Shipping
AL422V5 28pin plastic SOP +5 volt Replaced by AL422B
AL422V3 28pin plastic SOP +33 volt Replaced by AL422B
AL422

AL422B January 23 2001 5
50 Pinout Diagram



60 Pin Description

Pin name Pin # IO type Function
DI0~DI7 1~4 11~14 input Data input
WCK 9 Input Write clock
WE 5 Input (active low) Write enable
WRST 8 Input (active low) Write reset
DO0~DO7 15~18 25~28 Output (tristate) Data output
RCK 20 Input Read clock
RE 24 Input (active low) Read enable
RRST 21 Input (active low) Read reset
OE 22 Input (active low) Output enable
TST 7 Input Test pin (pulleddown)*
VDD 10 5V or 33V
DECVDD 19 Decoupling cap input
GND 6 23 Ground


1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DI0 DI1 DI2 DI3 WE GND TST WRST WCK VDD DI4 DI5 DI6 DI7
DO0 DO1 DO2 DO3 RE GND OE RRST RCK DEC DO4 DO5 DO6 DO7
AL42204 422B pinout diagram
AVERLOGIC
AL422B
XXXXX
XXXX
Lot Number
Date Code AL422

AL422B January 23 2001 6
70 Electrical Characteristics
71 Absolute Maximum Ratings
Ratings
Parameter
33V application 5V application
Unit
VDD Supply Voltage 10 ~ +45 10 ~ +70 V
VP Pin Voltage 10 ~ +55 10 ~ VDD +05 V
IO Output Current 20 ~ +20 20 ~ +20 mA
TAMB Ambient Op Temperature 0 ~ +70 0 ~ +70 °C
Tstg Storage temperature 55 ~ +125 55 ~ +125 °C


72 Recommended Operating Conditions
33V application 5V application
Parameter
Min Max Min Max
Unit
VDD Supply Voltage +30 +36 +45 +525 V
VIH High Level Input Voltage +20 +55 +30 VDD +05 V
VIL Low Level Input Voltage 10 +08 10 +08 V


73 DC Characteristics
(VDD 5V or 33V Vss0V TAMB 0 to 70°C)
33V application 5V application
Parameter
Min Typ Max Min Typ Max
Unit
IDD Operating Current @20MHz 33 50 mA
IDD Operating Current @30MHz 45 66 mA
IDD Operating Current @40MHz 57 82 mA
IDD Operating Current @50MHz 68 97 mA
IDDS Standby Current 7 12 mA
VOH Hilevel Output Voltage 07VDD VDD +30 VDD V
VOL Lolevel Output Voltage +04 +04 V
ILI Input Leakage Current 10 +10 10 +10 mA
ILO Output Leakage Current 10 +10 10 +10 mA AL422

AL422B January 23 2001 7
74 AC Characteristics
(VDD 5V or 33V Vss0V TAMB 0 to 70°C)
33V application 5V application
Parameter
Min Max Min Max
Unit
TWC WCK Cycle Time 20 1000 20 1000 ns
TWPH WCK High Pulse Width 7 7 ns
TWPL WCK Low Pulse Width 7 7 ns
TRC RCK Cycle Time 20 1000 20 1000 ns
TRPH RCK High Pulse Width 7 7 ns
TRPL RCK Low Pulse Width 7 7 ns
TAC Access Time 15 15 ns
TOH Output Hold Time 4 4 ns
THZ Output HighZ Setup Time 3 15 4 15 ns
TLZ Output LowZ Setup Time 3 15 4 15 ns
TWRS WRST Setup Time 5 6 ns
TWRH WRST Hold Time 2 3 ns
TRRS RRST Setup Time 5 6 ns
TRRH RRST Hold Time 2 3 ns
TDS Input Data Setup Time 5 6 ns
TDH Input Data Hold Time 2 3 ns
TWES WE Setup Time 5 6 ns
TWEH WE Hold Time 2 3 ns
TWPW WE Pulse Width 10 10 ns
TRES RE Setup Time 5 6 ns
TREH RE Hold Time 2 3 ns
TRPW RE Pulse Width 10 10 ns
TOES OE Setup Time 5 6 ns
TOEH OE Hold Time 2 3 ns
TOPW OE Pulse Width 10 10 ns
TTR Transition Time 2 20 3 20 ns
CI Input Capacitance 7 7 pF
CO Output Capacitance 7 7 pF
AL422

AL422B January 23 2001 8
· Input voltage levels are defined as VIH30V and VIL04V
· The read address needs to be at least 128 cycles after the write address


DO external load

AL422

AL422B January 23 2001 9
75 Timing Diagrams







cycle n Reset
cycle (s) cycle 0 cycle 1
WCK
WRST
DI7~0
AL42205 Write Cycle Timing (Write Reset)
TTR
TWRS TWRH
n1 n 0 1
TDS TDH
WE L
RCK
RRST
DO7~0 n1 n
TOH
AL42207 Read Cycle Timing (Read Reset)
TRPH
TRPL
0 1
cycle n Reset
cycle (s) cycle 0 cycle 1
TRRS TRRH
TAC
0
RE OE L AL422

AL422B January 23 2001 10











cycle n cycle n+1 cycle n+3
RCK
OE
DO7~0 n1 n
AL42209 Read Cycle Timing (Output Enable)
TRPH
TRPL
TOES TOEHTRC
n+1
TOPW
TOH
TAC
cycle n+2
HiZ
cycle n+4
n+4
THZ TLZ
RE L
cycle n cycle n+1 Disable cycle (s)
RCK
RE
DO7~0 n1 n
AL42208 Read Cycle Timing (Read Enable)
TRPH
TRPL
TRES TREHTRC
n+1
TRPW
TOH
TAC
n+2
cycle n+2
OE L AL422

AL422B January 23 2001 11







cycle n cycle n+1 Disable cycle (s)
WCK
WE
DI7~0 n1 n
TDS TDH
AL42206 Write Cycle Timing (Write Enable)
TWPH
TWPL
TWES TWEHTWC
n+1 n+2
TWPW
cycle n+2
cycle n cycle n+1 Disable cycle (s)
RCK
RE
DO7~0 n1 n
AL42214 Read Cycle Timing (RE RRST)
TRPH
TRPL
TRES TREH
TRC
n+1
TRPW
TOH
TAC
0
TRRS TRRH
RRST
cycle 0
OE L AL422

AL422B January 23 2001 12





cycle n cycle n+1 Disable cycle (s)
WCK
WE
DI7~0 n1 n
TDS TDH
AL42215 Write Cycle Timing (WE WRST)
TWPH
TWPL
TWES TWEH
TWC
n+1 1
TWPW
cycle 0
TWRS TWRH
WRST
0
cycle 1 AL422

AL422B January 23 2001 13
80 Functional Description
The AL422 is a video frame buffer consisting of DRAM that works like a FIFO which is long enough
to hold up to 819x480 bytes of picture information and fast enough to operate at 50MHz The
functional block diagram is as follows

The IO pinouts and functions are described as follows
DI7~DI0 Data Input Data is input on the rising edge of the cycle of WCK when WE is pulled low
(enabled)
DO7~DO0 Data Output Data output is synchronized with the RCK clock Data is obtained at the
rising edge of the RCK clock when RE is pulled low The access time is defined from the rising edge
of the RCK cycle
WCK Write Clock Input The write data input is synchronized with this clock Write data is input at
the rising edge of the WCK cycle when WE is pulled low (enabled) The internal write address
pointer is incremented automatically with this clock input
RCK Read Clock Input The read data output is synchronized with this clock Read data output at
the rising edge of the RCK cycle when OE is pulled low (enabled) The internal read address pointer
is incremented with this clock input
WE Write Enable Input WE controls the enablingdisabling of the data input When WE is
pulled low input data is acquired at the rising edge of the WCK cycle When WE is pulled high the
384k x8
Memory Cell Array
SRAM
Cache
Timing Generator
& Arbiter
Write
Address
Counter
Read
Address
Counter
Refresh Address
Counter
DI7~
DI0
DO7~
DO0
OE
RCK
RRST
RE
WCK
WRST
WE
AL42203 Block Diagram
Input
Buffer
Write
Data
Register
Read
Data
Register
Output
Buffer AL422

AL422B January 23 2001 14
memory does not accept data input The write address pointer is stopped at the current position WE
signal is fetched at the rising edge of the WCK cycle
RE Read Enable Input RE controls the operation of the data output When RE is pulled low
output data is provided at the rising edge of the RCK cycle and the internal read address is
incremented automatically RE signal is fetched at the rising edge of the RCK cycle
OE Output Enable Input OE controls the enablingdisabling of the data output When OE is
pulled low output data is provided at the rising edge of the RCK cycle When OE is pulled high data
output is disabled and the output pins remain at high impedance status OE signal is fetched at the
rising edge of RCK cycle
WRST Write Reset Input This reset signal initializes the write address to 0 and is fetched at the
rising edge of the WCK input cycle
RRST Write Reset Input This reset signal initializes the read address to 0 and is fetched at the
rising edge of the RCK input cycle
TST Test Pin For testing purpose only It should be pulled low for normal applications
DEC Decoupling cap pin should be connected to a 1mF or 22mF capacitor to ground for 5V
application For 33V application the DEC pin can be simply connected to the 33V power with
regular 01mF bypass capacitor

81 Memory Operation
Initialization
Apply WRST and RRST 01ms after power on then follow the following instructions for normal
operation
Reset Operation
The reset signal can be given at any time regardless of the WE RE and OE status however they
still need to meet the setup time and hold time requirements with reference to the clock input When
the reset signal is provided during disabled cycles the reset operation is not executed until cycles are
enabled again When WRST signal is pulled low the data input address will be set to 0 and the data
in the Input Buffer will be flushed into memory cell array When RRST signal is pulled low the data
output address will be set to 0 and prefetch the data from memory cell array to Output Buffer AL422

AL422B January 23 2001 15
Write Operation
Data input DI7~DI0 is written into the write register at the WCK input when WE is pulled low The
write data should meet the setup time and hold time requirements with reference to the WCK input
cycle
Write operation is prohibited when WE is pulled high and the write address pointer is stopped at the
current position The write address starts from there when the WE is pulled low again The WE
signal needs to meet the setup time and hold time requirements with reference to the WCK input cycle
Read Operation
Data output DO7~DO0 is written into the read register at the RCK input when both RE and OE are
pulled low The output data is ready after TAC (access time) from the rising edge of the RCK input
cycle
The read address pointer is stopped at the current position when RE is pulled high and starts there
when RE is pulled low again
OE needs to be pulled low for read operations When OE is pulled high the data outputs will be at
high impedance stage The read address pointer still increases synchronously with RCK regardless of
the OE status The RE and OE signals need to meet the setup time and hold time requirements with
reference to the RCK input cycle
When the new data is read the read address should be between 128 to 393247 cycles after the write
address otherwise the output may not be new data

82 5V and 33V applications
The AL422 can accept either 33V or 5V power with slightly different external configuration The
internal voltage regulator can convert 5V power to 33V for the embedded DRAM and logic circuitry
when 5V power is applied to VDD pin (#10) only and leave the DEC pin (#19) decoupled by a
capacitor of 1mF or 22mF to ground The regulator can also be bypassed when 33V power is applied
to both VDD and DEC pins In either case the AL422 is 5V or 33V IO tolerant The 33V
configuration consumes less power and is free from noise interference from the voltage regulator so
may be more ideal for highspeed applications
Please note that using the AL422B with 5V configuration can directly replace the previous AL422V5
using it with 33V configuration can directly replace the previous AL422V3 No additional
modification is required AL422

AL422B January 23 2001 16
The 5V configuration (direct replacement of the previous AL422V5) is as follows


The 33V configuration (direct replacement of the previous AL422V3) is as follows
83 Application Notes
831 Irregular ReadWrite
It is recommended that the WCK and RCK are kept running at least 1MHz at all times The faster one
of WCK and RCK is used as the DRAM refresh timing clock and has to be kept free running When
irregular FIFO IO control is needed keep the clock free running and use WE or RE to control the
IO as follows

The following drawing shows irregular clock and should be avoided

VDD DEC
5V
AL422B
01uF 22uF
VDD DEC
33V
AL422B
33V
01uF 01uF
10 19
Data
WE
AL42217 Slow Write Correct
WCK AL422

AL422B January 23 2001 17


832 The Proper Manipulation of FIFO Access
The FIFO memory is designed to allow easy field delay timebase conversion and other types of
signal processing To ensure the expectant data can be read out from the AL422 FIFO the proper
manipulation on the AL422 FIFO memory is highly recommended

1 The read address should be between 128 to 393247 cycles after the write address to read the
current field data (The restriction is indicated in the Read Operation Section)

2 The proper FIFO access must make sure after read reset the read operation will either read all the
old data (last field data) until next read reset or follow the constraint 1 above to read newly update
data In any 2 read resets interval the FIFO access can not read old data (the field data are written
before last write reset) and stop for a period then read the newly update data (even at that time
write counter is ahead of read counter by more than 128 cycles)

If the FIFO memory manipulations violate the above conditions some amount of consecutive
unexpected data (old data) will be read at the FIFO data bus

833 Single Field Write with Multiple Read Operation
It is one of the functions for FIFO memory that can buffer a field data and do multiple times of fields
read access In some applications such as still image capturing require one field write and multiple
field data read operations In order not to violate the 128 cycles of write to read delay latency rule
the write address (pointer) needs to be reset to 0 for the coming multiple read operations so that FIFO
can provide the expectant data at DO bus

834 One Field Delay Line (The Old Data Read)
As the design shown in diagram by applying the reset every 1field cycle (with the common signal for
WRST and RRST) and a constant readwrite operation (with all WE RE and OE are tied to
ground) 1 field delay line timing is shown in timing chart below When the difference between the
Data
WE
AL42216 Slow Write Incorrect
WCK AL422

AL422B January 23 2001 18
write address and the read address is 0 (the read address and the write address are the same) the old
field data are read as shown in the timing chart





















AL422 1 Field Delay Line Diagram
8bit Input 8bit OutputDI[70]
AL422
WE
WCK
DO[70]
RE
RCK
Reset
Clock
OE
RRSTWRST
RCK
WCK
RRST
WRST
DI7~0 0
AL42208 1 Field Delay Line Timing Diagram
1 n
cycle 0 cycle 1 cycle n
DO7~0
0
0
Field m Field m + 1
1
1
cycle 0
tAC
Data of field m
cycle 1 AL422

AL422B January 23 2001 19

90 Mechanical Drawing
28 PIN PLASTIC SOP







CONTACT INFORMATION




AverLogic Technologies Inc
6840 Via Del Oro
Suite 160
San Jose CA 95119
USA





Tel 1 408 3610400
Fax 1 408 3610404
Email sales@averlogiccom
URL wwwaverlogiccom


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