XX学院
课程设计报告
题 目 Verilog hdl课程设计
专 业 动化
学生姓名
指导教师
完成时间 2015
课程设计（报告）务书
（理 工 科 类）
课程设计（报告）题目：
电子琴设计
课程设计（文）工作容
课程设计目标
1培养综合运知识独立开展实践创新力
2深入学Verilog HDL解编程环境
3学会运ModelsimQuartus II等编程仿真软件
4硬件语言编程硬件实物功演示相结合加深理解Verilog HDL学
二研究方法手段应
1务分成干模块查阅相关文资料分模块调试完成务
2遇问题组成员时讨出解决方法
3遇组解决问题时组交流询问老师
4程序仿真仿真问题进行模块调试根实验箱硬件实现否符合求检验程序正确否
三课程设计预期效果
1完成实验环境搭建
2具手动弹奏动播放功
3键（开关）作琴键少通蜂鸣器输出7音阶
4动播放曲目少两首
摘
简易电子琴设计通通软硬件结合实现硬件系统包括控器芯片9键LED蜂鸣器等软件资源包括编写Verilog HDL程序应软件Modelsim仿真软件Quartus II电子琴键代琴键弹奏功动播放功键七音动播放功中三首曲子分两老虎天空城康定情歌程序五模块分模块琴键模块曲1模块曲2模块曲3模块硬件实现三LED灯组合亮暗分表示七键情况外两键选择曲目实验箱原始时钟50MHz分频变成频率输出通蜂鸣器输出频率声音音乐节拍通分频变4Hz作14拍通模块调模块实现电子琴功
关键词Verilog HDL 电子琴 模块 分频
ABSTRACT
This article introduced the simple electric piano’s design It realizes through the software and hardware union The hardware system includes a director 9 keys LEDs and a buzzer The software design uses Verilog HDL Emulation uses Quartus II It can broadcast the system establishment the corresponding note and can complete a military song the broadcast but also has shows the sound the function Designs the simple electric piano to have in the hardware The program has seven modules including main module fractional frequency module and so on Keyboard with keys to play the function and replace the keys to play function Key has seven sound automatic playback function with three in song were the two tiger the sky city and kangding love songs Software has its merit It is perfect in the software Verilog HDL The original frequency is divided into different frequencys The piano makes sound by the buzzer with different frequencys
keywordsVerilog HDL electric piano module fractional frequency
第章 系统设计
第节 课题目标总体方案
次项目设计课程目标学Verilog HDL基础更加深入理解硬件设计语言功作特征动手力创新力结合起次电子琴实验目标：
1具手动弹奏动播放功
2键（开关）作琴键少通蜂鸣器输出7音阶
3动播放曲目少两首
次实验方框图：（模块中分频）
模块
九键
Key1Key7弹奏
Key8Key9（mm）选择歌曲
mm00
键模块
Key1
Key7
模块名digital_piano
mm01
曲目1两老虎
模块名 bell
mm10
曲目2康定情歌
模块名 bell2
mm11
曲目3天空城
模块名 bell3
第二节 设计框图说明
模块
模块中mm(key8key9)值选择调模块mm01调曲目1模块bell模块mm10调曲目2模块bell2模块mm11调曲目3模块bell3模块key8key9没情况程序调键模块digital_piano模块
module main(inclkoutclkkey1key2key3key4key5key6key7key8key9num)
input inclk
input key1key2key3key4key5key6key7key8key9
output outclk
output[30]num
reg outclkclk_6M
reg [30]c
wire out1out2out3out4
wire[80] key
reg [10]mm
assign key {key1key2key3key4key5key6key7key8key9} 键拼键变量key
调子调块
digital_piano m1(inclk(inclk)key1(key1)key2(key2)key3(key3)key4(key4)
key5(key5)key6(key6)key7(key7)beep2(out2)num(num))
bell m2(inclk(inclk)beep1(out1))
bell2 m3(inclk(inclk)beep3(out3))
bell3 m4(inclk(inclk)beep4(out4))
always @(posedge clk_6M) 时钟升检测否键
begin
if(key 9＇b111111110)
mm < 2＇b01
else if(key9＇b111111101)
mm < 2＇b10
else if(key9＇b111111100)
mm < 2＇b11
else mm < 2＇b00
end
always@(posedge inclk)
begin
if(c<4＇d4)
c else
begin
c<4＇d0
clk_6M~clk_6M
end
end
always @(posedge clk_6M)
begin
if(mm 2＇b01)
outclk < out1
else if(mm 2＇b00)
outclk < out2
else if(mm 2＇b10)
outclk < out3
else outclk < out4
end
endmodule
二键模块
Key1key7应dosi七音模拟电子琴弹奏
digital_piano子模块
module digital_piano(inclkkey1key2key3key4key5key6key7beep2num)
input inclkkey1key2key3key4key5key6key7
output[30]num
output beep2
wire [60] key_code
reg [30]c
reg clk_6M
reg beep_r
reg [30]num
reg [150] count
reg [150] count_end
parameter Do 7＇b1111110 状态机7编码分应中音7音符
re 7＇b1111101
mi 7＇b1111011
fa 7＇b1110111
so 7＇b1101111
la 7＇b1011111
si 7＇b0111111
assign key_code {key7key6key5key4key3key2key1}
assign beep2 beep_r 输出音乐
always@(posedge inclk)
begin
if(c<4＇d4)
c else
begin
c<4＇d0
clk_6M~clk_6M
end
end
always@(posedge clk_6M) 分频模块出乐谱
begin
count < count + 16＇d1 计数器加1
if(count count_end)
begin
count <16＇d0 计数器清零
beep_r < beep_r
end
end
always@(posedge clk_6M) 状态机根键状态选择音符输出
begin
case(key_code)
Do count_end < 16＇d11450
re count_end < 16＇d10204
mi count_end < 16＇d09090
fa count_end < 16＇d08571
so count_end < 16＇d07802
la count_end < 16＇d06802
si count_end < 16＇d06060
defaultcount_end < 16＇d0
endcase
end
always @ (posedge clk_6M)
begin
case(key_code)
Do num<4＇b0001
re num<4＇b0010
mi num<4＇b0011
fa num<4＇b0100
so num<4＇b0101
la num<4＇b0110
si num<4＇b0111
endcase
end
endmodule
二 曲目1模块
bell子模块 两老虎
module bell (inclkbeep1)
input inclk 系统时钟
output beep1 蜂鸣器输出端
reg [30]highmedlow
reg [150]origin
reg beep_r 寄存器
reg [70]state
reg [150]count
assign beep1beep_r 输出音乐
时钟频率6MHz
reg clk_6MHz
reg [20] cnt1
always@(posedge inclk)
begin
if(cnt1<3＇d4)
cnt1 else
begin
cnt1<3＇b0
clk_6MHz<~clk_6MHz
end
end
时钟频率4MHz
reg clk_4Hz
reg [240] cnt2
always@(posedge inclk)
begin
if(cnt2<25＇d6250000)
cnt2 else
begin
cnt2<25＇b0
clk_4Hz<~clk_4Hz
end
end
always @(posedge clk_6MHz)
begin
count < count + 1＇b1 计数器加1
if(count origin)
begin
count < 16＇h0 计数器清零
beep_r < beep_r 输出取反
end
end
always@(posedge clk_4Hz)
begin
case({highmedlow})
12＇b000000010000origin11466mid1
12＇b000000100000origin10216mid2
12＇b000000110000origin9101mid3
12＇b000001000000origin8590mid4
12＇b000001010000origin7653mid5
12＇b000001100000origin6818mid6
12＇b000000000101origin14447low5
endcase
end
always @(posedge clk_4Hz) 歌曲 <>
begin
if(state 63) state 0计时实现循环演奏
else
state state + 1
case(state)
01 {highmedlow}12＇b000000010000mid1
23 {highmedlow}12＇b000000100000mid2
45 {highmedlow}12＇b000000110000mid3
67 {highmedlow}12＇b000000010000mid1
89 {highmedlow}12＇b000000010000mid1
1011 {highmedlow}12＇b000000100000mid2
1213 {highmedlow}12＇b000000110000mid3
1415 {highmedlow}12＇b000000010000mid1
1617 {highmedlow}12＇b000000110000mid3
1819 {highmedlow}12＇b000001000000mid4
20212223 {highmedlow}12＇b000001010000mid5
2425 {highmedlow}12＇b000000110000mid3
2627 {highmedlow}12＇b000001000000mid4
28293031 {highmedlow}12＇b000001010000mid5
32 {highmedlow}12＇b000001010000mid5
33 {highmedlow}12＇b000001100000mid6
34 {highmedlow}12＇b000001010000mid5
35 {highmedlow}12＇b000001000000mid4
3637 {highmedlow}12＇b000000110000mid3
3839 {highmedlow}12＇b000000010000mid1
40 {highmedlow}12＇b000001010000mid5
41 {highmedlow}12＇b000001100000mid6
42 {highmedlow}12＇b000001010000mid5
43 {highmedlow}12＇b000001000000mid4
4445 {highmedlow}12＇b000000110000mid3
4647 {highmedlow}12＇b000000010000mid1
4849 {highmedlow}12＇b000000100000mid2
5051 {highmedlow}12＇b000000000101low5
52535455 {highmedlow}12＇b000000010000mid1
5656 {highmedlow}12＇b000000100000mid2
5758 {highmedlow}12＇b000000000101low5
5960616263 {highmedlow}12＇b000000010000mid1
default {highmedlow}12＇bx
endcase
end
endmodule
三 曲目2模块
bell2子模块康定情歌
module bell2 (inclkbeep3)
input inclk 系统时钟
output beep3 蜂鸣器输出端
reg [30]highmedlow
reg [150]origin
reg beep_r 寄存器
reg [70]state
reg [150]count
assign beep3beep_r 输出音乐
时钟频率6MHz
reg clk_6MHz
reg [20] cnt1
always@(posedge inclk)
begin
if(cnt1<3＇d4)
cnt1 else
begin
cnt1<3＇b0
clk_6MHz<~clk_6MHz
end
end
时钟频率4MHz
reg clk_4Hz
reg [240] cnt2
always@(posedge inclk)
begin
if(cnt2<25＇d6250000)
cnt2 else
begin
cnt2<25＇b0
clk_4Hz<~clk_4Hz
end
end
always @(posedge clk_6MHz)
begin
count < count + 1＇b1 计数器加1
if(count origin)
begin
count < 16＇h0 计数器清零
beep_r < beep_r 输出取反
end
end
always@(posedge clk_4Hz)
begin
case({highmedlow})
＇b000000000001origin22900 低1
＇b000000000010origin20408 低2
＇b000000000011origin18181 低3
＇b000000000101origin15267 低5
＇b000000000110origin13605 低6
＇b000000000111origin11472 中1
＇b000000100000origin10216 中2
＇b000000110000origin9101 中3
＇b000001010000origin7653 中5
＇b000001100000origin6818 中6
＇b000100000000origin5733 高1
＇b001000000000origin5108 高2
＇b001100000000origin4551 高3
endcase
end
always @(posedge clk_4Hz)
begin
if(state 103)
state 0
else
state state + 1 康定情歌
case(state)
01 {highmedlow}＇b000000110000中3
23 {highmedlow}＇b000001010000中5
45 {highmedlow}＇b000001100000中6
6 {highmedlow}＇b000001100000中6
7 {highmedlow}＇b000001010000中5
8910 {highmedlow}＇b000001100000中6
11 {highmedlow}＇b000000110000中3
12131415 {highmedlow}＇b000000100000中2
1617 {highmedlow}＇b000000110000中3
1819 {highmedlow}＇b000001010000中5
2021 {highmedlow}＇b000001100000中6
22 {highmedlow}＇b000001100000中6
23 {highmedlow}＇b000001010000中5
2425 {highmedlow}＇b000001100000中6
262728293031{highmedlow}＇b000000110000中3
3233 {highmedlow}＇b000000110000中3
3435 {highmedlow}＇b000001010000中5
3637 {highmedlow}＇b000001100000中6
38 {highmedlow}＇b000001100000中6
39 {highmedlow}＇b000001010000中5
404142 {highmedlow}＇b000001100000中6
43 {highmedlow}＇b000000110000中3
44454647 {highmedlow}＇b000000100000中2
4849 {highmedlow}＇b000000000101中5
5051 {highmedlow}＇b000000110000中3
52 {highmedlow}＇b000000100000中2
53 {highmedlow}＇b000000110000中3
54 {highmedlow}＇b000000100000中2
55 {highmedlow}＇b0000000001111
5657 {highmedlow}＇b000000100000中2
585960616263{highmedlow}＇b000000000110低6
6465 {highmedlow}＇b000001100000中6
666768697071{highmedlow}＇b000000100000中2
7273 {highmedlow}＇b000000000101中5
747576777879{highmedlow}＇b000000110000中3
80 {highmedlow}＇b000000100000中2
81 {highmedlow}＇b0000000001111
828384858687{highmedlow}＇b000001100000中6
8889 {highmedlow}＇b000000000101中5
9091 {highmedlow}＇b000000110000中3
92 {highmedlow}＇b000000100000中2
93 {highmedlow}＇b000000110000中3
94 {highmedlow}＇b000000100000中2
95 {highmedlow}＇b0000000001111
9697 {highmedlow}＇b000000100000中2
9899100101102103{highmedlow}＇b000001100000中6
endcase
end
endmodule
四 曲目3模块
bell3子模块天空城
module bell3 (inclkbeep4)
input inclk 系统时钟
output beep4 蜂鸣器输出端
reg [30]highmedlow
reg [150]origin
reg beep_r 寄存器
reg [70]state
reg [150]count
assign beep4beep_r 输出音乐
时钟频率6MHz
reg clk_6MHz
reg [20] cnt1
always@(posedge inclk)
begin
if(cnt1<3＇d4)
cnt1 else
begin
cnt1<3＇b0
clk_6MHz<~clk_6MHz
end
end
时钟频率4MHz
reg clk_4Hz
reg [240] cnt2
always@(posedge inclk)
begin
if(cnt2<25＇d6250000)
cnt2 else
begin
cnt2<25＇b0
clk_4Hz<~clk_4Hz
end
end
always @(posedge clk_6MHz)
begin
count < count + 1＇b1 计数器加1
if(count origin)
begin
count < 16＇h0 计数器清零
beep_r < beep_r 输出取反
end
end
always@(posedge clk_4Hz)
begin
case({highmedlow})
＇b000000000001origin22900 低1
＇b000000000010origin20408 低2
＇b000000000011origin18181 低3
＇b000000000100origin17142 低4
＇b000000000101origin15267 低5
＇b000000000110origin13605 低6
＇b000000000111origin12121 低7
＇b000000000111origin11472 中1
＇b000000100000origin10216 中2
＇b000000110000origin9101 中3
＇b000000111000origin8571 中4
＇b000001010000origin7653 中5
＇b000001100000origin6818 中6
＇b000010000000origin6060 中7
＇b000100000000origin5733 高1
＇b001000000000origin5108 高2
＇b001100000000origin4551 高3
＇b001010000000origin4294 高4
＇b010000000000origin3826 高5
＇b011000000000origin3409 高6
＇b010100000000origin3050 高7
endcase
end
always @(posedge clk_4Hz)
begin
if(state 195)state 0
else
state state + 1 kang ding qing ge
case(state)
0 {highmedlow}＇b000001100000中6
1 {highmedlow}＇b000010000000中7
234 {highmedlow}＇b000100000000高1
5 {highmedlow}＇b000010000000中7
67 {highmedlow}＇b000100000000高1
89 {highmedlow}＇b001100000000高3
101112131415
{highmedlow}＇b000010000000中7
1617 {highmedlow}＇b000000110000中3
181920 {highmedlow}＇b000001100000中6
21 {highmedlow}＇b000001010000中5
2223 {highmedlow}＇b000001100000中6
2425 {highmedlow}＇b000000000111中1
262728293031
{highmedlow}＇b000001010000中5
32 {highmedlow}＇b000000110000中3
33 {highmedlow}＇b000000110000中3
343536 {highmedlow}＇b000000111000中4
37 {highmedlow}＇b000000110000中3
38 {highmedlow}＇b000000111000中4
394041 {highmedlow}＇b000100000000高1
424344 {highmedlow}＇b000000110000中3
454647 {highmedlow}＇b000100000000高1
484950 {highmedlow}＇b000010000000中7
515253 {highmedlow}＇b000000111000中4
5455565758596061
{highmedlow}＇b000010000000中7
62 {highmedlow}＇b000001100000中6
63 {highmedlow}＇b000010000000中7
646566 {highmedlow}＇b000100000000高1
67 {highmedlow}＇b010100000000高7
6869 {highmedlow}＇b000100000000高1
7071 {highmedlow}＇b001100000000高3
727374 {highmedlow}＇b000010000000中7
7576 {highmedlow}＇b000000110000中3
777879 {highmedlow}＇b000001100000中6
80 {highmedlow}＇b000000000101中5
8182 {highmedlow}＇b000001100000中6
8384 {highmedlow}＇b000000000111中1
858687888990
{highmedlow}＇b000001010000中5
91 {highmedlow}＇b000000110000中3
92 {highmedlow}＇b000000110000中3
9394 {highmedlow}＇b000000111000中4
95 {highmedlow}＇b000100000000高1
969798 {highmedlow}＇b000010000000中7
99100 {highmedlow}＇b000100000000高1
101102 {highmedlow}＇b001000000000高2
103 {highmedlow}＇b001100000000高3
104105106107108109
{highmedlow}＇b000100000000高1
110 {highmedlow}＇b000010000000中7
111112 {highmedlow}＇b000001100000中6
113114 {highmedlow}＇b000010000000中7
115116 {highmedlow}＇b000001010000中5
117118119120121122
{highmedlow}＇b000001100000中6
123124 {highmedlow}＇b000000000111中1
125 {highmedlow}＇b001000000000高2
126127128 {highmedlow}＇b001100000000高3
129 {highmedlow}＇b001000000000高2
130131 {highmedlow}＇b001100000000高3
132133 {highmedlow}＇b010000000000高5
134135136137138139
{highmedlow}＇b001000000000高2
140141 {highmedlow}＇b000001010000中5
142143144 {highmedlow}＇b000100000000高1
145 {highmedlow}＇b000010000000中7
146147 {highmedlow}＇b000100000000高1
148149150151152153154155
{highmedlow}＇b001100000000高3
156157 {highmedlow}＇b000001100000中6
158159 {highmedlow}＇b000010000000中7
160161162163
{highmedlow}＇b000100000000高1
164165 {highmedlow}＇b000010000000中7
166167 {highmedlow}＇b000100000000高1
168169 {highmedlow}＇b001000000000高2
170171172 {highmedlow}＇b000100000000高1
173174175176177178
{highmedlow}＇b000001010000中5
179180 {highmedlow}＇b001010000000高4
181182 {highmedlow}＇b001100000000高3
183184185 {highmedlow}＇b001000000000高2
186187 {highmedlow}＇b000100000000高1
188189190191192193194195
{highmedlow}＇b001100000000高3
endcase
end
endmodule
第二章 结果讨
第二节 调试结果问题分析
实验时ModelSim编译软件初写时编译出许错误端口属性定义错误语法错误等
硬件调试时发现蜂鸣器发出七基音标准细程序发现分频数扩倍导致音调准确改正蜂鸣器发声基标准
进行口连接时口部分设置颠倒key1key7发音序错误doremifasolasi序发音
心体会
实次试验中老师指出程序中许足处例：程序中时序问题程序行问题等等外次实验quartusII软件软件熟悉导致许错误问题发生通次实验熟悉quartusII软件解开发基流程方法进步加深Verilog编程语言理解
次硬件课设程中越越认识点编程项目实现着关重硬件开发程中更应该重视编程编程作完善开发缺少部分次次反复设计证测试中提高逻辑分析力全面分析问题力发现问题解决问题力然设计程非常烦琐磨练意志通方面资料收集知识面进步拓宽时发现足语言表达较差更清楚表达意思逻辑分析力提高够编程力足预先想法未实现发现问题事方面努力加改进系统结构设计长路需走需时间积累
硬件仿真程中明白团队合作重性时候旦遇困难时候需时间搞懂团队中通讨解决
总言次实验非常意义仅Verilog HDL理解加强力锻炼学生活工作中极帮助
参考文献
[1] 夏宇闻．第二版Verilog 数字系统设计教程．北京：北京航空航天学出版社2008．
[2] 杨晓慧 杨旭 编著．FPGA系统设计实例．北京：民邮电出版社2010
[3] 罗杰 谢美 编著．电子线路设计实验测试．北京：电子工业出版社2008．
[4] 杜慧敏 李宥谋 赵全良 编著．基VerilogFPGA设计基础．西安： 西安电子科技学2006．
附 录
分频览表
音阶应频率（时钟频率50MHz分6Hz）
音阶
频率Hz
周期us
半周期us
分频数
中音
1
523
1912
956
11472
2
578
1684
842
10380
3
659
1518
759
9104
4
698
1432
716
8595
5
784
1276
638
7653
6
880
1136
568
6818
7
988
1012
506
6073
高音
H1
1046
956
478
5736
H2
1175
852
426
5106
二 频率分频数转换
三 实验仿真图
四 脚配置
五EDA实验箱引脚说明
1时钟引脚分配：Pin 28
2系统频率：50 MHz
3拨码开关：拨0拨1
开关
开关1
开关2
开关3
开关4
开关5
开关6
开关7
开关8
引脚
Pin 64
Pin 65
Pin 66
Pin 67
Pin 68
Pin 73
Pin 74
Pin 75
4 键开关： 0初始1
开关
Key1
Key2
Key3
Key4
Key5
Key6
Key7
Key8
Reset
引脚
Pin64
Pin 65
Pin 66
Pin 67
Pin 68
Pin 73
Pin74
Pin 75
Pin76
58LED应引脚分配：
LED
Led1
Led 2
Led 3
Led 4
Led 5
Led 6
Led 7
Led 8
引脚
Pin 2
Pin 1
Pin 61
Pin 62
Pin 63
Pin 184
Pin 182
Pin 181
6蜂鸣器BEEP引脚分配：Pin 117
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XX学院
课程设计报告
题 目 Verilog hdl课程设计
专 业 动化
学生姓名
指导教师
完成时间 2015
课程设计（报告）务书
（理 工 科 类）
课程设计（报告）题目：
电子琴设计
课程设计（文）工作容
课程设计目标
1培养综合运知识独立开展实践创新力
2深入学Verilog HDL解编程环境
3学会运ModelsimQuartus II等编程仿真软件
4硬件语言编程硬件实物功演示相结合加深理解Verilog HDL学
二研究方法手段应
1务分成干模块查阅相关文资料分模块调试完成务
2遇问题组成员时讨出解决方法
3遇组解决问题时组交流询问老师
4程序仿真仿真问题进行模块调试根实验箱硬件实现否符合求检验程序正确否
三课程设计预期效果
1完成实验环境搭建
2具手动弹奏动播放功
3键（开关）作琴键少通蜂鸣器输出7音阶
4动播放曲目少两首
摘
简易电子琴设计通通软硬件结合实现硬件系统包括控器芯片9键LED蜂鸣器等软件资源包括编写Verilog HDL程序应软件Modelsim仿真软件Quartus II电子琴键代琴键弹奏功动播放功键七音动播放功中三首曲子分两老虎天空城康定情歌程序五模块分模块琴键模块曲1模块曲2模块曲3模块硬件实现三LED灯组合亮暗分表示七键情况外两键选择曲目实验箱原始时钟50MHz分频变成频率输出通蜂鸣器输出频率声音音乐节拍通分频变4Hz作14拍通模块调模块实现电子琴功
关键词Verilog HDL 电子琴 模块 分频
ABSTRACT
This article introduced the simple electric piano’s design It realizes through the software and hardware union The hardware system includes a director 9 keys LEDs and a buzzer The software design uses Verilog HDL Emulation uses Quartus II It can broadcast the system establishment the corresponding note and can complete a military song the broadcast but also has shows the sound the function Designs the simple electric piano to have in the hardware The program has seven modules including main module fractional frequency module and so on Keyboard with keys to play the function and replace the keys to play function Key has seven sound automatic playback function with three in song were the two tiger the sky city and kangding love songs Software has its merit It is perfect in the software Verilog HDL The original frequency is divided into different frequencys The piano makes sound by the buzzer with different frequencys
keywordsVerilog HDL electric piano module fractional frequency
第章 系统设计
第节 课题目标总体方案
次项目设计课程目标学Verilog HDL基础更加深入理解硬件设计语言功作特征动手力创新力结合起次电子琴实验目标：
1具手动弹奏动播放功
2键（开关）作琴键少通蜂鸣器输出7音阶
3动播放曲目少两首
次实验方框图：（模块中分频）
模块
九键
Key1Key7弹奏
Key8Key9（mm）选择歌曲
mm00
键模块
Key1
Key7
模块名digital_piano
mm01
曲目1两老虎
模块名 bell
mm10
曲目2康定情歌
模块名 bell2
mm11
曲目3天空城
模块名 bell3
第二节 设计框图说明
模块
模块中mm(key8key9)值选择调模块mm01调曲目1模块bell模块mm10调曲目2模块bell2模块mm11调曲目3模块bell3模块key8key9没情况程序调键模块digital_piano模块
module main(inclkoutclkkey1key2key3key4key5key6key7key8key9num)
input inclk
input key1key2key3key4key5key6key7key8key9
output outclk
output[30]num
reg outclkclk_6M
reg [30]c
wire out1out2out3out4
wire[80] key
reg [10]mm
assign key {key1key2key3key4key5key6key7key8key9} 键拼键变量key
调子调块
digital_piano m1(inclk(inclk)key1(key1)key2(key2)key3(key3)key4(key4)
key5(key5)key6(key6)key7(key7)beep2(out2)num(num))
bell m2(inclk(inclk)beep1(out1))
bell2 m3(inclk(inclk)beep3(out3))
bell3 m4(inclk(inclk)beep4(out4))
always @(posedge clk_6M) 时钟升检测否键
begin
if(key 9＇b111111110)
mm < 2＇b01
else if(key9＇b111111101)
mm < 2＇b10
else if(key9＇b111111100)
mm < 2＇b11
else mm < 2＇b00
end
always@(posedge inclk)
begin
if(c<4＇d4)
c
begin
c<4＇d0
clk_6M~clk_6M
end
end
always @(posedge clk_6M)
begin
if(mm 2＇b01)
outclk < out1
else if(mm 2＇b00)
outclk < out2
else if(mm 2＇b10)
outclk < out3
else outclk < out4
end
endmodule
二键模块
Key1key7应dosi七音模拟电子琴弹奏
digital_piano子模块
module digital_piano(inclkkey1key2key3key4key5key6key7beep2num)
input inclkkey1key2key3key4key5key6key7
output[30]num
output beep2
wire [60] key_code
reg [30]c
reg clk_6M
reg beep_r
reg [30]num
reg [150] count
reg [150] count_end
parameter Do 7＇b1111110 状态机7编码分应中音7音符
re 7＇b1111101
mi 7＇b1111011
fa 7＇b1110111
so 7＇b1101111
la 7＇b1011111
si 7＇b0111111
assign key_code {key7key6key5key4key3key2key1}
assign beep2 beep_r 输出音乐
always@(posedge inclk)
begin
if(c<4＇d4)
c
begin
c<4＇d0
clk_6M~clk_6M
end
end
always@(posedge clk_6M) 分频模块出乐谱
begin
count < count + 16＇d1 计数器加1
if(count count_end)
begin
count <16＇d0 计数器清零
beep_r < beep_r
end
end
always@(posedge clk_6M) 状态机根键状态选择音符输出
begin
case(key_code)
Do count_end < 16＇d11450
re count_end < 16＇d10204
mi count_end < 16＇d09090
fa count_end < 16＇d08571
so count_end < 16＇d07802
la count_end < 16＇d06802
si count_end < 16＇d06060
defaultcount_end < 16＇d0
endcase
end
always @ (posedge clk_6M)
begin
case(key_code)
Do num<4＇b0001
re num<4＇b0010
mi num<4＇b0011
fa num<4＇b0100
so num<4＇b0101
la num<4＇b0110
si num<4＇b0111
endcase
end
endmodule
二 曲目1模块
bell子模块 两老虎
module bell (inclkbeep1)
input inclk 系统时钟
output beep1 蜂鸣器输出端
reg [30]highmedlow
reg [150]origin
reg beep_r 寄存器
reg [70]state
reg [150]count
assign beep1beep_r 输出音乐
时钟频率6MHz
reg clk_6MHz
reg [20] cnt1
always@(posedge inclk)
begin
if(cnt1<3＇d4)
cnt1
begin
cnt1<3＇b0
clk_6MHz<~clk_6MHz
end
end
时钟频率4MHz
reg clk_4Hz
reg [240] cnt2
always@(posedge inclk)
begin
if(cnt2<25＇d6250000)
cnt2
begin
cnt2<25＇b0
clk_4Hz<~clk_4Hz
end
end
always @(posedge clk_6MHz)
begin
count < count + 1＇b1 计数器加1
if(count origin)
begin
count < 16＇h0 计数器清零
beep_r < beep_r 输出取反
end
end
always@(posedge clk_4Hz)
begin
case({highmedlow})
12＇b000000010000origin11466mid1
12＇b000000100000origin10216mid2
12＇b000000110000origin9101mid3
12＇b000001000000origin8590mid4
12＇b000001010000origin7653mid5
12＇b000001100000origin6818mid6
12＇b000000000101origin14447low5
endcase
end
always @(posedge clk_4Hz) 歌曲 <
begin
if(state 63) state 0计时实现循环演奏
else
state state + 1
case(state)
01 {highmedlow}12＇b000000010000mid1
23 {highmedlow}12＇b000000100000mid2
45 {highmedlow}12＇b000000110000mid3
67 {highmedlow}12＇b000000010000mid1
89 {highmedlow}12＇b000000010000mid1
1011 {highmedlow}12＇b000000100000mid2
1213 {highmedlow}12＇b000000110000mid3
1415 {highmedlow}12＇b000000010000mid1
1617 {highmedlow}12＇b000000110000mid3
1819 {highmedlow}12＇b000001000000mid4
20212223 {highmedlow}12＇b000001010000mid5
2425 {highmedlow}12＇b000000110000mid3
2627 {highmedlow}12＇b000001000000mid4
28293031 {highmedlow}12＇b000001010000mid5
32 {highmedlow}12＇b000001010000mid5
33 {highmedlow}12＇b000001100000mid6
34 {highmedlow}12＇b000001010000mid5
35 {highmedlow}12＇b000001000000mid4
3637 {highmedlow}12＇b000000110000mid3
3839 {highmedlow}12＇b000000010000mid1
40 {highmedlow}12＇b000001010000mid5
41 {highmedlow}12＇b000001100000mid6
42 {highmedlow}12＇b000001010000mid5
43 {highmedlow}12＇b000001000000mid4
4445 {highmedlow}12＇b000000110000mid3
4647 {highmedlow}12＇b000000010000mid1
4849 {highmedlow}12＇b000000100000mid2
5051 {highmedlow}12＇b000000000101low5
52535455 {highmedlow}12＇b000000010000mid1
5656 {highmedlow}12＇b000000100000mid2
5758 {highmedlow}12＇b000000000101low5
5960616263 {highmedlow}12＇b000000010000mid1
default {highmedlow}12＇bx
endcase
end
endmodule
三 曲目2模块
bell2子模块康定情歌
module bell2 (inclkbeep3)
input inclk 系统时钟
output beep3 蜂鸣器输出端
reg [30]highmedlow
reg [150]origin
reg beep_r 寄存器
reg [70]state
reg [150]count
assign beep3beep_r 输出音乐
时钟频率6MHz
reg clk_6MHz
reg [20] cnt1
always@(posedge inclk)
begin
if(cnt1<3＇d4)
cnt1
begin
cnt1<3＇b0
clk_6MHz<~clk_6MHz
end
end
时钟频率4MHz
reg clk_4Hz
reg [240] cnt2
always@(posedge inclk)
begin
if(cnt2<25＇d6250000)
cnt2
begin
cnt2<25＇b0
clk_4Hz<~clk_4Hz
end
end
always @(posedge clk_6MHz)
begin
count < count + 1＇b1 计数器加1
if(count origin)
begin
count < 16＇h0 计数器清零
beep_r < beep_r 输出取反
end
end
always@(posedge clk_4Hz)
begin
case({highmedlow})
＇b000000000001origin22900 低1
＇b000000000010origin20408 低2
＇b000000000011origin18181 低3
＇b000000000101origin15267 低5
＇b000000000110origin13605 低6
＇b000000000111origin11472 中1
＇b000000100000origin10216 中2
＇b000000110000origin9101 中3
＇b000001010000origin7653 中5
＇b000001100000origin6818 中6
＇b000100000000origin5733 高1
＇b001000000000origin5108 高2
＇b001100000000origin4551 高3
endcase
end
always @(posedge clk_4Hz)
begin
if(state 103)
state 0
else
state state + 1 康定情歌
case(state)
01 {highmedlow}＇b000000110000中3
23 {highmedlow}＇b000001010000中5
45 {highmedlow}＇b000001100000中6
6 {highmedlow}＇b000001100000中6
7 {highmedlow}＇b000001010000中5
8910 {highmedlow}＇b000001100000中6
11 {highmedlow}＇b000000110000中3
12131415 {highmedlow}＇b000000100000中2
1617 {highmedlow}＇b000000110000中3
1819 {highmedlow}＇b000001010000中5
2021 {highmedlow}＇b000001100000中6
22 {highmedlow}＇b000001100000中6
23 {highmedlow}＇b000001010000中5
2425 {highmedlow}＇b000001100000中6
262728293031{highmedlow}＇b000000110000中3
3233 {highmedlow}＇b000000110000中3
3435 {highmedlow}＇b000001010000中5
3637 {highmedlow}＇b000001100000中6
38 {highmedlow}＇b000001100000中6
39 {highmedlow}＇b000001010000中5
404142 {highmedlow}＇b000001100000中6
43 {highmedlow}＇b000000110000中3
44454647 {highmedlow}＇b000000100000中2
4849 {highmedlow}＇b000000000101中5
5051 {highmedlow}＇b000000110000中3
52 {highmedlow}＇b000000100000中2
53 {highmedlow}＇b000000110000中3
54 {highmedlow}＇b000000100000中2
55 {highmedlow}＇b0000000001111
5657 {highmedlow}＇b000000100000中2
585960616263{highmedlow}＇b000000000110低6
6465 {highmedlow}＇b000001100000中6
666768697071{highmedlow}＇b000000100000中2
7273 {highmedlow}＇b000000000101中5
747576777879{highmedlow}＇b000000110000中3
80 {highmedlow}＇b000000100000中2
81 {highmedlow}＇b0000000001111
828384858687{highmedlow}＇b000001100000中6
8889 {highmedlow}＇b000000000101中5
9091 {highmedlow}＇b000000110000中3
92 {highmedlow}＇b000000100000中2
93 {highmedlow}＇b000000110000中3
94 {highmedlow}＇b000000100000中2
95 {highmedlow}＇b0000000001111
9697 {highmedlow}＇b000000100000中2
9899100101102103{highmedlow}＇b000001100000中6
endcase
end
endmodule
四 曲目3模块
bell3子模块天空城
module bell3 (inclkbeep4)
input inclk 系统时钟
output beep4 蜂鸣器输出端
reg [30]highmedlow
reg [150]origin
reg beep_r 寄存器
reg [70]state
reg [150]count
assign beep4beep_r 输出音乐
时钟频率6MHz
reg clk_6MHz
reg [20] cnt1
always@(posedge inclk)
begin
if(cnt1<3＇d4)
cnt1
begin
cnt1<3＇b0
clk_6MHz<~clk_6MHz
end
end
时钟频率4MHz
reg clk_4Hz
reg [240] cnt2
always@(posedge inclk)
begin
if(cnt2<25＇d6250000)
cnt2
begin
cnt2<25＇b0
clk_4Hz<~clk_4Hz
end
end
always @(posedge clk_6MHz)
begin
count < count + 1＇b1 计数器加1
if(count origin)
begin
count < 16＇h0 计数器清零
beep_r < beep_r 输出取反
end
end
always@(posedge clk_4Hz)
begin
case({highmedlow})
＇b000000000001origin22900 低1
＇b000000000010origin20408 低2
＇b000000000011origin18181 低3
＇b000000000100origin17142 低4
＇b000000000101origin15267 低5
＇b000000000110origin13605 低6
＇b000000000111origin12121 低7
＇b000000000111origin11472 中1
＇b000000100000origin10216 中2
＇b000000110000origin9101 中3
＇b000000111000origin8571 中4
＇b000001010000origin7653 中5
＇b000001100000origin6818 中6
＇b000010000000origin6060 中7
＇b000100000000origin5733 高1
＇b001000000000origin5108 高2
＇b001100000000origin4551 高3
＇b001010000000origin4294 高4
＇b010000000000origin3826 高5
＇b011000000000origin3409 高6
＇b010100000000origin3050 高7
endcase
end
always @(posedge clk_4Hz)
begin
if(state 195)state 0
else
state state + 1 kang ding qing ge
case(state)
0 {highmedlow}＇b000001100000中6
1 {highmedlow}＇b000010000000中7
234 {highmedlow}＇b000100000000高1
5 {highmedlow}＇b000010000000中7
67 {highmedlow}＇b000100000000高1
89 {highmedlow}＇b001100000000高3
101112131415
{highmedlow}＇b000010000000中7
1617 {highmedlow}＇b000000110000中3
181920 {highmedlow}＇b000001100000中6
21 {highmedlow}＇b000001010000中5
2223 {highmedlow}＇b000001100000中6
2425 {highmedlow}＇b000000000111中1
262728293031
{highmedlow}＇b000001010000中5
32 {highmedlow}＇b000000110000中3
33 {highmedlow}＇b000000110000中3
343536 {highmedlow}＇b000000111000中4
37 {highmedlow}＇b000000110000中3
38 {highmedlow}＇b000000111000中4
394041 {highmedlow}＇b000100000000高1
424344 {highmedlow}＇b000000110000中3
454647 {highmedlow}＇b000100000000高1
484950 {highmedlow}＇b000010000000中7
515253 {highmedlow}＇b000000111000中4
5455565758596061
{highmedlow}＇b000010000000中7
62 {highmedlow}＇b000001100000中6
63 {highmedlow}＇b000010000000中7
646566 {highmedlow}＇b000100000000高1
67 {highmedlow}＇b010100000000高7
6869 {highmedlow}＇b000100000000高1
7071 {highmedlow}＇b001100000000高3
727374 {highmedlow}＇b000010000000中7
7576 {highmedlow}＇b000000110000中3
777879 {highmedlow}＇b000001100000中6
80 {highmedlow}＇b000000000101中5
8182 {highmedlow}＇b000001100000中6
8384 {highmedlow}＇b000000000111中1
858687888990
{highmedlow}＇b000001010000中5
91 {highmedlow}＇b000000110000中3
92 {highmedlow}＇b000000110000中3
9394 {highmedlow}＇b000000111000中4
95 {highmedlow}＇b000100000000高1
969798 {highmedlow}＇b000010000000中7
99100 {highmedlow}＇b000100000000高1
101102 {highmedlow}＇b001000000000高2
103 {highmedlow}＇b001100000000高3
104105106107108109
{highmedlow}＇b000100000000高1
110 {highmedlow}＇b000010000000中7
111112 {highmedlow}＇b000001100000中6
113114 {highmedlow}＇b000010000000中7
115116 {highmedlow}＇b000001010000中5
117118119120121122
{highmedlow}＇b000001100000中6
123124 {highmedlow}＇b000000000111中1
125 {highmedlow}＇b001000000000高2
126127128 {highmedlow}＇b001100000000高3
129 {highmedlow}＇b001000000000高2
130131 {highmedlow}＇b001100000000高3
132133 {highmedlow}＇b010000000000高5
134135136137138139
{highmedlow}＇b001000000000高2
140141 {highmedlow}＇b000001010000中5
142143144 {highmedlow}＇b000100000000高1
145 {highmedlow}＇b000010000000中7
146147 {highmedlow}＇b000100000000高1
148149150151152153154155
{highmedlow}＇b001100000000高3
156157 {highmedlow}＇b000001100000中6
158159 {highmedlow}＇b000010000000中7
160161162163
{highmedlow}＇b000100000000高1
164165 {highmedlow}＇b000010000000中7
166167 {highmedlow}＇b000100000000高1
168169 {highmedlow}＇b001000000000高2
170171172 {highmedlow}＇b000100000000高1
173174175176177178
{highmedlow}＇b000001010000中5
179180 {highmedlow}＇b001010000000高4
181182 {highmedlow}＇b001100000000高3
183184185 {highmedlow}＇b001000000000高2
186187 {highmedlow}＇b000100000000高1
188189190191192193194195
{highmedlow}＇b001100000000高3
endcase
end
endmodule
第二章 结果讨
第二节 调试结果问题分析
实验时ModelSim编译软件初写时编译出许错误端口属性定义错误语法错误等
硬件调试时发现蜂鸣器发出七基音标准细程序发现分频数扩倍导致音调准确改正蜂鸣器发声基标准
进行口连接时口部分设置颠倒key1key7发音序错误doremifasolasi序发音
心体会
实次试验中老师指出程序中许足处例：程序中时序问题程序行问题等等外次实验quartusII软件软件熟悉导致许错误问题发生通次实验熟悉quartusII软件解开发基流程方法进步加深Verilog编程语言理解
次硬件课设程中越越认识点编程项目实现着关重硬件开发程中更应该重视编程编程作完善开发缺少部分次次反复设计证测试中提高逻辑分析力全面分析问题力发现问题解决问题力然设计程非常烦琐磨练意志通方面资料收集知识面进步拓宽时发现足语言表达较差更清楚表达意思逻辑分析力提高够编程力足预先想法未实现发现问题事方面努力加改进系统结构设计长路需走需时间积累
硬件仿真程中明白团队合作重性时候旦遇困难时候需时间搞懂团队中通讨解决
总言次实验非常意义仅Verilog HDL理解加强力锻炼学生活工作中极帮助
参考文献
[1] 夏宇闻．第二版Verilog 数字系统设计教程．北京：北京航空航天学出版社2008．
[2] 杨晓慧 杨旭 编著．FPGA系统设计实例．北京：民邮电出版社2010
[3] 罗杰 谢美 编著．电子线路设计实验测试．北京：电子工业出版社2008．
[4] 杜慧敏 李宥谋 赵全良 编著．基VerilogFPGA设计基础．西安： 西安电子科技学2006．
附 录
分频览表
音阶应频率（时钟频率50MHz分6Hz）
音阶
频率Hz
周期us
半周期us
分频数
中音
1
523
1912
956
11472
2
578
1684
842
10380
3
659
1518
759
9104
4
698
1432
716
8595
5
784
1276
638
7653
6
880
1136
568
6818
7
988
1012
506
6073
高音
H1
1046
956
478
5736
H2
1175
852
426
5106
二 频率分频数转换
三 实验仿真图
四 脚配置
五EDA实验箱引脚说明
1时钟引脚分配：Pin 28
2系统频率：50 MHz
3拨码开关：拨0拨1
开关
开关1
开关2
开关3
开关4
开关5
开关6
开关7
开关8
引脚
Pin 64
Pin 65
Pin 66
Pin 67
Pin 68
Pin 73
Pin 74
Pin 75
4 键开关： 0初始1
开关
Key1
Key2
Key3
Key4
Key5
Key6
Key7
Key8
Reset
引脚
Pin64
Pin 65
Pin 66
Pin 67
Pin 68
Pin 73
Pin74
Pin 75
Pin76
58LED应引脚分配：
LED
Led1
Led 2
Led 3
Led 4
Led 5
Led 6
Led 7
Led 8
引脚
Pin 2
Pin 1
Pin 61
Pin 62
Pin 63
Pin 184
Pin 182
Pin 181
6蜂鸣器BEEP引脚分配：Pin 117
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